Icestorm: SUBS (uxtw, 32-bit) measurements

Code:

  subs w0, w0, w1, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  subs w0, w0, w1, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10109	251598	10108	10210	20220	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	252592	10221	10322	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10205	10060	10117	10117	10148	251774	10108	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	253256	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010

Test 3: Latency 1->3

Code:

  subs w0, w1, w0, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10107	251562	10109	10210	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	253129	10030	10030	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10025	10060	10035	10035	10068	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs w0, w1, w2, uxtw
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519291	20107	20214	30224	20001	20100
20204	20030	20101	20101	20108	519434	20107	20214	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519507	20017	20032	30044	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20134	20053	20053	20098	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30087	20022	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs w0, w1, w2, uxtw
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519416	20107	20212	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30290	20015	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	0	0	20018	0	519638	20018	20036	30020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	0	0	20010	0	519598	20010	20020	30020	20001	20010

Test 6: throughput

Count: 8

Code:

  subs w0, w8, w9, uxtw
  subs w1, w8, w9, uxtw
  subs w2, w8, w9, uxtw
  subs w3, w8, w9, uxtw
  subs w4, w8, w9, uxtw
  subs w5, w8, w9, uxtw
  subs w6, w8, w9, uxtw
  subs w7, w8, w9, uxtw

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5010

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	40092	80111	80111	80114	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80205	40106	80140	80140	80147	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	40212	80031	80031	80034	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80025	40067	80062	80062	80070	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010

SUBS (uxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations