Icestorm: ADCS (64-bit) measurements

Code:

  adcs x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000

Test 2: Latency 1->2

Code:

  adcs x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	251520	10106	10206	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253284	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010

Test 3: Latency 1->3

Code:

  adcs x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10109	251520	10106	10206	30224	10001	10100
10204	10030	10101	10101	10108	251658	10106	10206	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	253256	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253239	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010

Test 4: Latency 1->4

Chain cycles: 1

Code:

  adcs x0, x1, x2
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20201	20201	20209	508681	20208	20208	40216	20101	10100
20204	20030	20201	20201	20211	509018	20208	20208	40224	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20205	20060	20215	20215	20246	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20021	20021	20031	509756	20030	20032	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010

Test 5: Latency 4->2

Chain cycles: 1

Code:

  adcs x0, x1, x2
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519413	20107	20214	40232	20001	20100
20204	20030	20101	20101	20107	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40514	20069	20100
20204	20229	20185	20185	20284	520470	20195	20308	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20080	20122	20122	20152	520006	20154	20262	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	520019	20152	20262	40232	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40140	20015	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010

Test 6: Latency 4->3

Chain cycles: 1

Code:

  adcs x0, x1, x2
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519434	20107	20212	40228	20001	20100
20204	20030	20101	20101	20108	519434	20107	20214	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20205	20060	20115	20115	20148	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519411	20018	20036	40044	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519956	20058	20080	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010

Test 7: Latency 4->4

Code:

  adcs x0, x1, x2

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10208	252858	10208	10208	30230	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	253235	10029	10032	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010

Test 8: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  adcs x0, x8, x9
  ands xzr, xzr, xzr
  adcs x1, x8, x9
  ands xzr, xzr, xzr
  adcs x2, x8, x9
  ands xzr, xzr, xzr
  adcs x3, x8, x9
  ands xzr, xzr, xzr
  adcs x4, x8, x9
  ands xzr, xzr, xzr
  adcs x5, x8, x9
  ands xzr, xzr, xzr
  adcs x6, x8, x9
  ands xzr, xzr, xzr
  adcs x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7992

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	64049	160114	160114	160120	682098	160115	160216	240287	160050	80100
160204	63952	160113	160113	160119	682244	160115	160216	240224	160011	80100
160204	63941	160111	160111	160118	682079	160116	160216	240230	160011	80100
160204	63933	160115	160115	160119	682170	160119	160220	240230	160015	80100
160204	63937	160113	160113	160119	682089	160118	160220	240230	160011	80100
160204	63937	160111	160111	160115	681997	160116	160216	240230	160015	80100
160204	63937	160111	160111	160115	682079	160116	160216	240230	160015	80100
160204	63937	160111	160111	160115	682253	160118	160220	240230	160015	80100
160204	63938	160113	160113	160117	682147	160115	160216	240230	160015	80100
160205	63957	160149	160149	160156	682227	160115	160216	240230	160015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7985

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	65616	160023	160023	160028	0	681800	0	160010	160020	0	240020	160001	80010
160024	63981	160011	160011	160010	0	682382	0	160010	160020	0	240020	160001	80010
160024	63952	160011	160011	160010	0	682748	0	160010	160020	0	240020	160001	80010
160024	63886	160011	160011	160010	0	686037	0	160010	160020	0	240020	160001	80010
160024	63891	160011	160011	160010	0	678861	0	160010	160020	0	240020	160001	80010
160024	63868	160011	160011	160010	0	682500	0	160010	160020	0	240020	160001	80010
160024	63884	160011	160011	160010	0	682402	0	160010	160020	0	240020	160001	80010
160024	63878	160011	160011	160010	0	682595	0	160010	160020	0	240077	160036	80010
160024	63888	160011	160011	160010	0	682798	0	160010	160020	0	240020	160001	80010
160024	63789	160011	160011	160010	0	685966	0	160010	160020	0	240020	160001	80010

Test 9: throughput

Count: 4

Code:

  fcmp s0, s0
  adcs x0, x4, x5
  adcs x1, x4, x5
  adcs x2, x4, x5
  adcs x3, x4, x5

Initialization

  mov x4, 5
  mov x5, 6
  mov x6, 7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6208

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24911	50109	40106	10003	40114	10004	0	314904	0	40017	50116	40212	0	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	0	309222	0	40017	50116	40212	0	10004	120236	20008	40002	40100
50204	24831	50104	40101	10003	40112	10004	0	309222	0	40017	50116	40212	0	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	0	309224	0	40017	50116	40212	0	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	0	309222	0	40017	50116	40212	0	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	0	309222	0	40017	50116	40212	0	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	0	309222	0	40017	50116	40212	0	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	0	310052	0	40106	50233	40307	0	10026	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	0	309222	0	40017	50116	40212	0	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	0	309222	0	40017	50116	40212	0	10004	120236	20008	40001	40100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6197

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24850	50016	40014	10002	40024	10004	312049	40017	50026	40032	10004	120020	20000	40001	40010
50024	24790	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	120020	20000	40001	40010

Test 10: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  adcs x0, x7, x8
  adcs x1, x7, x8
  adcs x2, x7, x8
  adcs x3, x7, x8
  adcs x4, x7, x8
  adcs x5, x7, x8
  adcs x6, x7, x8

Initialization

  mov x7, 8
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5844

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	40922	80110	80110	80116	540886	80116	80216	210242	80010	70100
80204	40905	80107	80107	80112	540336	80156	80256	210230	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	80112	541028	80112	80212	210230	80007	70100
80204	40886	80110	80110	80116	541972	80148	80248	210230	80007	70100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5839

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80025	40845	80058	80058	80073	541748	80036	80036	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40797	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40845	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010

ADCS (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: Latency 4->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 9: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 10: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations