Icestorm: LDRSH (pre-index, 32-bit) measurements

Code:

  ldrsh w0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1397	2073	1043	1030	1042	1000	20821	17547	2000	1000	1000	1000	1000	1001	1000	1000
2004	1064	2001	1001	1000	1000	1000	21208	17540	2000	1000	1000	1000	1000	1001	1000	1000
2004	1093	2001	1001	1000	1000	1000	21067	17573	2000	1000	1000	1000	1000	1001	1000	1000
2004	1063	2001	1001	1000	1000	1000	21073	17641	2000	1000	1000	1000	1000	1001	1000	1000
2004	1073	2001	1001	1000	1000	1000	21182	17529	2000	1000	1000	1000	1000	1001	1000	1000
2004	1064	2001	1001	1000	1000	1000	21166	17342	2000	1000	1000	1000	1000	1001	1000	1000
2004	1061	2001	1001	1000	1000	1000	20808	17574	2000	1000	1000	1000	1000	1001	1000	1000
2004	1080	2001	1001	1000	1000	1000	21290	17472	2000	1000	1000	1000	1000	1001	1000	1000
2004	1089	2001	1001	1000	1000	1000	21079	17434	2000	1000	1000	1000	1000	1001	1000	1000
2004	1079	2001	1001	1000	1000	1000	21555	17909	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0285

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71290	50162	40157	10005	40247	10002	1852045	535249	50108	40211	10003	70221	10004	40007	10000	40100
50204	70166	50107	40107	10000	40106	10003	1851927	535276	50109	40212	10004	70221	10004	40007	10000	40100
50204	70205	50107	40107	10000	40106	10003	1853061	535652	50109	40212	10004	70221	10004	40007	10000	40100
50204	70226	50107	40107	10000	40106	10003	1852278	535395	50109	40212	10004	70221	10004	40007	10000	40100
50204	70164	50107	40107	10000	40106	10003	1851927	535276	50109	40212	10004	70221	10004	40007	10000	40100
50204	70164	50107	40107	10000	40106	10003	1851927	535276	50109	40212	10004	70221	10004	40007	10000	40100
50204	70164	50107	40107	10000	40106	10003	1851927	535276	50109	40212	10004	70221	10004	40007	10000	40100
50204	70164	50107	40107	10000	40106	10003	1851927	535276	50109	40212	10004	70221	10004	40007	10000	40100
50204	70164	50107	40107	10000	40106	10003	1853412	535769	50109	40212	10004	70221	10004	40007	10000	40100
50204	70164	50107	40107	10000	40106	10003	1851927	535276	50109	40212	10004	70221	10004	40007	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0123

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71248	50069	40064	10005	40156	10003	1851995	535580	50019	40032	10004	70020	10000	40004	10000	40010
50024	70127	50014	40014	10000	40010	10003	1851531	535451	50019	40032	10004	70020	10000	40004	10000	40010
50024	70123	50014	40014	10000	40010	10000	1850876	535267	50010	40020	10000	70020	10000	40004	10000	40010
50024	70121	50014	40014	10000	40010	10000	1850822	535249	50010	40020	10000	70020	10000	40004	10000	40010
50024	70121	50014	40014	10000	40010	10000	1850876	535267	50010	40020	10000	70020	10000	40005	10000	40010
50024	70123	50014	40014	10000	40010	10000	1850822	535249	50010	40020	10000	70020	10000	40004	10000	40010
50024	70123	50014	40014	10000	40010	10000	1850876	535267	50010	40020	10000	70020	10000	40004	10000	40010
50024	70123	50014	40014	10000	40010	10000	1850822	535249	50010	40020	10000	70020	10000	40004	10000	40010
50025	70222	50028	40026	10002	40050	10000	1851092	535341	50010	40020	10000	70109	10013	40015	10000	40010
50024	70138	50014	40014	10000	40010	10000	1851065	535318	50010	40020	10000	70020	10000	40004	10000	40010

Test 3: throughput

Count: 8

Code:

  ldrsh w0, [x6, #8]!
  ldrsh w0, [x7, #8]!
  ldrsh w0, [x8, #8]!
  ldrsh w0, [x9, #8]!
  ldrsh w0, [x10, #8]!
  ldrsh w0, [x11, #8]!
  ldrsh w0, [x12, #8]!
  ldrsh w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5402

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160209	44204	160411	80313	80098	80316	80012	240581	641257	160125	80213	80013	80212	80012	0	80009	80000	0	80100
160204	43228	160109	80109	80000	80112	80009	240485	634299	160121	80212	80012	80212	80012	0	80009	80000	0	80100
160204	43216	160109	80109	80000	80112	80011	240485	646011	160123	80212	80012	80212	80012	0	80009	80000	0	80100
160204	43217	160109	80109	80000	80112	80009	240485	642890	160121	80212	80012	80212	80012	0	80009	80000	0	80100
160204	43217	160110	80109	80001	80112	80009	240479	643901	160119	80210	80010	80212	80012	0	80009	80000	0	80100
160204	43217	160110	80109	80001	80112	80012	240485	639288	160124	80212	80012	80212	80012	0	80009	80000	0	80100
160204	43217	160109	80109	80000	80112	80012	240485	644229	160124	80212	80012	80212	80012	0	80009	80000	0	80100
160204	43234	160113	80109	80004	80112	80008	240485	644676	160120	80212	80012	83095	82650	66	81544	81351	38	82330
160204	43237	160109	80109	80000	80112	80011	240485	636091	160123	80212	80012	80212	80012	0	80009	80000	0	80100
160204	43217	160109	80109	80000	80112	80011	240485	646568	160123	80212	80012	80212	80012	0	80009	80000	0	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5403

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44442	160341	80222	80119	80225	80011	240340	645265	160033	80032	80012	80020	80000	80001	80000	80010
160024	43230	160011	80011	80000	80010	80000	240223	643959	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	641244	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80054	240627	621189	160118	80074	80054	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	646673	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	645408	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	641276	160010	80020	80000	80020	80000	80001	80000	80010
160024	43227	160011	80011	80000	80010	80000	240223	639056	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	641123	160010	80020	80000	80020	80000	80001	80000	80010
160024	43224	160011	80011	80000	80010	80000	240223	645797	160010	80020	80000	80020	80000	80001	80000	80010

LDRSH (pre-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations