Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CBNZ (not taken)

Test 1: uops

Code:

  cbnz x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	9401	5306	5306	7182	4509	1503	1509	1003	1
1004	4082	1032	1032	1038	3000	1000	1000	1000	1
1004	2459	1001	1001	1000	3000	1000	1000	1000	1
1004	2503	1001	1001	1000	3000	1000	1000	1000	1
1004	2438	1001	1001	1000	3000	1000	1000	1000	1
1004	2805	1001	1001	1000	3000	1000	1000	1000	1
1004	2776	1001	1001	1000	3000	1000	1000	1000	1
1004	2618	1001	1001	1000	3000	1000	1000	1000	1
1004	2497	1001	1001	1000	3000	1000	1000	1000	1
1004	2738	1001	1001	1000	3000	1000	1000	1000	1

Test 2: throughput

Count: 8

Code:

  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4

Initialization

  mov x0, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5836

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	52883	83513	83513	85011	241848	80616	80882	80378	1	100
80204	46764	80154	80154	80177	240456	80152	80264	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80626	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5837

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	118697	117121	117121	132992	249192	83064	83869	81888	0	0	1	0	0	10
80024	124426	119963	119963	137155	246546	82182	82793	81494	0	0	1	0	0	10
80024	47679	80611	80611	80879	240186	80062	80092	80020	0	0	1	0	0	10
80024	46695	80011	80011	80010	240030	80010	80020	80020	0	0	1	0	0	10
80024	46695	80011	80011	80010	240030	80010	80020	80020	0	0	1	0	0	10
80024	46695	80011	80011	80010	240030	80010	80020	80020	0	0	1	0	0	10
80024	46695	80011	80011	80010	240030	80010	80020	80020	0	0	1	0	0	10
80024	46695	80011	80011	80010	240030	80010	80020	80020	0	0	1	0	0	10
80024	46695	80011	80011	80010	240030	80010	80020	80020	0	0	1	0	0	10
80024	46695	80011	80011	80010	240030	80010	80020	80020	0	0	1	0	0	10