Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STNP (64-bit)

Test 1: uops

Code:

  stnp x0, x1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1154	1019	1	1018	1000	17421	1000	1000	3000	1	1000
1004	1068	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000

Test 2: throughput

Code:

  stnp x0, x1, [x6]
  add x6, x6, 16

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0060

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20214	11285	20702	10522	10180	10523	10003	45202	171286	20110	10209	10009	10209	30027	10006	10000	10100
20204	10065	20105	10105	10000	10106	10001	85968	170320	20107	10206	10006	10206	30018	10005	10000	10100
20204	10060	20105	10105	10000	10106	10001	85968	170320	20107	10206	10006	10206	30018	10005	10000	10100
20204	10060	20105	10105	10000	10106	10001	85968	170320	20107	10206	10006	10206	30018	10005	10000	10100
20204	10060	20105	10105	10000	10106	10001	85968	170320	20107	10206	10006	10206	30018	10005	10000	10100
20204	10060	20105	10105	10000	10106	10001	85968	170320	20107	10206	10006	10206	30018	10005	10000	10100
20204	10060	20105	10105	10000	10106	10001	85968	170320	20107	10206	10006	10206	30018	10005	10000	10100
20204	10060	20105	10105	10000	10106	10001	85968	170320	20107	10206	10006	10206	30018	10005	10000	10100
20204	10120	20105	10105	10000	10106	10001	85968	170320	20107	10206	10006	10206	30018	10005	10000	10100
20204	10060	20105	10105	10000	10106	10001	64316	172858	20107	10206	10006	10206	30018	10005	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0102

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20034	11521	20607	10427	10180	10428	10003	48944	171389	20020	10027	10008	10020	30000	10001	10000	10010
20024	10119	20011	10011	10000	10010	10000	50819	171055	20010	10020	10000	10020	30000	10001	10000	10010
20024	10101	20011	10011	10000	10010	10000	48967	171055	20010	10020	10000	10020	30000	10001	10000	10010
20024	10101	20011	10011	10000	10010	10000	50819	171055	20010	10020	10000	10020	30000	10001	10000	10010
20024	10111	20011	10011	10000	10010	10000	50819	171595	20010	10020	10000	10020	30000	10001	10000	10010
20024	10111	20011	10011	10000	10010	10000	38992	173125	20010	10020	10000	10020	30000	10001	10000	10010
20024	10121	20011	10011	10000	10010	10000	50819	171415	20010	10020	10000	10020	30000	10001	10000	10010
20024	10101	20011	10011	10000	10010	10000	50819	171055	20010	10020	10000	10020	30000	10001	10000	10010
20024	10101	20011	10011	10000	10010	10000	50819	171055	20010	10020	10000	10020	30000	10001	10000	10010
20024	10101	20011	10011	10000	10010	10000	50819	171055	20010	10020	10000	10020	30000	10001	10000	10010

Test 3: throughput

Code:

  stnp x0, x1, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0408

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10205	10152	10119	101	10018	100	10001	300	176446	10101	200	10008	200	30024	1	10000	100
10204	10408	10101	101	10000	100	10001	300	176544	10101	200	10008	200	30024	1	10000	100
10204	10408	10101	101	10000	100	10001	300	176544	10101	200	10008	200	30024	1	10000	100
10204	10408	10101	101	10000	100	10001	300	176544	10101	200	10008	200	30024	1	10000	100
10204	10408	10101	101	10000	100	10001	300	176544	10101	200	10008	200	30024	1	10000	100
10204	10408	10101	101	10000	100	10001	300	176544	10101	200	10008	200	30024	1	10000	100
10205	10429	10120	103	10017	102	10001	300	176544	10101	200	10008	200	30024	1	10000	100
10204	10408	10101	101	10000	100	10001	300	176544	10101	200	10008	200	30024	1	10000	100
10204	10408	10101	101	10000	100	10001	300	176544	10101	200	10008	200	30024	1	10000	100
10204	10408	10101	101	10000	100	10001	300	176544	10101	200	10008	200	30024	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0401

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10025	10146	10029	11	10018	10	10001	30	176508	10011	20	10008	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176541	10010	20	10000	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10030	30	176406	10040	20	10044	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176541	10010	20	10000	20	30000	1	10000	10
10024	10401	10011	11	10000	10	10000	30	176541	10010	20	10000	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176399	10010	20	10000	20	30000	1	10000	10
10024	10401	10011	11	10000	10	10000	30	176399	10010	20	10000	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176399	10010	20	10000	20	30000	1	10000	10
10024	10401	10011	11	10000	10	10000	30	176399	10010	20	10000	20	30000	1	10000	10
10024	10401	10011	11	10000	10	10000	30	176399	10010	20	10000	20	30000	1	10000	10