Icestorm: CCMP (register, 64-bit) measurements

Code:

  ccmp x0, x1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  ccmp x0, x1, #0, hi
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	0	519311	0	20107	20214	0	40232	20001	10100
20205	20060	20115	20115	20148	0	519548	0	20108	20216	0	40232	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	40232	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	40232	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	40232	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	40232	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	40232	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	40232	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	40232	20001	10100
20204	20030	20101	20101	20108	0	519548	0	20108	20216	0	40232	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519516	20018	20034	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40140	20015	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  ccmp x0, x1, #0, hi
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519338	20108	20214	40228	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519866	20148	20264	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010

Test 4: Latency 3->3

Code:

  ccmp x0, x1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10208	254716	10212	10214	30242	10101	100
10204	10030	10201	10201	10211	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	255052	10029	10030	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10025	10060	10035	10035	10069	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ccmp x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, x1, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, x1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7889

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160204	63310	160114	160114	160118	688477	160120	160222	240239	0	160019	0	100
160204	63136	160112	160112	160117	690058	160118	160218	240236	0	160014	0	100
160204	63143	160108	160108	160115	692303	160120	160220	240230	0	160013	0	100
160204	63129	160112	160112	160118	686358	160118	160220	240224	0	160011	0	100
160204	63134	160114	160114	160120	671516	160119	160221	240230	0	160010	0	100
160204	63127	160112	160112	160118	686358	160118	160220	240224	0	160011	0	100
160204	63160	160112	160112	160118	691305	160123	160224	240230	0	160012	0	100
160204	63098	160112	160112	160118	686358	160118	160220	240236	0	160014	0	100
160204	63118	160112	160112	160118	691935	160118	160220	240230	0	160012	0	100
160204	63081	160114	160114	160120	687919	160118	160220	240224	0	160011	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7830

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	64591	160026	160026	160033	690571	160010	160020	240020	160001	10
160024	63199	160011	160011	160010	671270	160064	160076	240020	160001	10
160024	62727	160011	160011	160010	671333	160010	160020	240020	160001	10
160024	62554	160011	160011	160010	670248	160010	160020	240020	160001	10
160024	62646	160011	160011	160010	671641	160010	160020	240020	160001	10
160024	62519	160011	160011	160010	669667	160010	160020	240020	160001	10
160024	62564	160011	160011	160010	669982	160010	160020	240020	160001	10
160025	62708	160061	160061	160068	671474	160010	160020	240020	160001	10
160024	62566	160011	160011	160010	669464	160010	160020	240020	160001	10
160024	62631	160011	160011	160010	671884	160010	160020	240020	160001	10

Test 6: throughput

Count: 4

Code:

  fcmp s0, s0
  ccmp x0, x1, #0, hi
  ccmp x0, x1, #0, hi
  ccmp x0, x1, #0, hi
  ccmp x0, x1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24024	50105	40102	10003	40112	10004	315845	40022	50122	40217	10005	120242	20008	40004	100
50204	24004	50106	40103	10003	40112	10004	315126	40017	50118	40214	10004	120248	20010	40004	100
50204	23993	50103	40101	10002	40109	10003	314822	40017	50116	40212	10004	120227	20006	40003	100
50204	23979	50106	40103	10003	40109	10003	315434	40012	50112	40209	10003	120227	20006	40001	100
50204	23994	50105	40102	10003	40112	10004	315617	40017	50116	40212	10004	120236	20008	40002	100
50204	23983	50103	40101	10002	40109	10003	315110	40017	50116	40212	10004	120236	20008	40002	100
50204	23991	50103	40101	10002	40112	10004	315137	40017	50116	40212	10004	120227	20006	40001	100
50204	23984	50103	40101	10002	40109	10003	315896	40017	50116	40212	10004	120248	20008	40007	100
50204	24013	50104	40101	10003	40112	10004	315287	40012	50112	40209	10003	120236	20008	40002	100
50204	23991	50103	40101	10002	40112	10004	315271	40018	50116	40212	10004	120236	20008	40001	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24153	50017	40014	10003	40022	10004	316945	40000	50010	40020	10000	120020	20000	40001	10
50024	23976	50011	40011	10000	40010	10000	315482	40000	50010	40020	10000	120020	20000	40001	10
50024	24027	50011	40011	10000	40010	10000	316143	40000	50010	40020	10000	120020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	315966	40000	50010	40020	10000	120020	20000	40001	10
50024	24002	50011	40011	10000	40010	10000	316531	40000	50010	40020	10000	120020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	315457	40000	50010	40020	10000	120020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	316681	40000	50010	40020	10000	120158	20024	40025	10
50024	24051	50011	40011	10000	40010	10000	316096	40000	50010	40020	10000	120020	20000	40001	10
50024	23992	50011	40011	10000	40010	10000	315621	40000	50010	40020	10000	120020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	316360	40000	50010	40020	10000	120020	20000	40001	10

Test 7: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  ccmp x0, x1, #0, hi
  ccmp x0, x1, #0, hi
  ccmp x0, x1, #0, hi
  ccmp x0, x1, #0, hi
  ccmp x0, x1, #0, hi
  ccmp x0, x1, #0, hi
  ccmp x0, x1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5568

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	39015	80104	80104	80111	547994	80114	80214	210221	80003	100
80204	38932	80107	80107	80113	549924	80268	80369	210242	80004	100
80204	38970	80104	80104	80114	549465	80111	80212	210221	80003	100
80205	39028	80140	80140	80152	549021	80114	80216	210242	80005	100
80204	38941	80106	80106	80114	548963	80116	80216	210242	80004	100
80204	38997	80103	80103	80111	549465	80111	80212	210230	80004	100
80204	39003	80104	80104	80111	549137	80108	80208	210230	80003	100
80204	39009	80106	80106	80116	549968	80111	80212	210242	80006	100
80204	38969	80103	80103	80111	549657	80111	80212	210230	80003	100
80204	39004	80103	80103	80111	549608	80111	80212	210242	80008	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5557

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	39097	80027	80027	80035	0	548681	0	0	80020	80020	0	0	210020	80011	10
80024	38900	80021	80021	80020	0	547121	0	0	80020	80020	0	0	210020	80011	10
80024	38924	80021	80021	80020	0	545912	0	0	80020	80020	0	0	210020	80011	10
80024	38932	80021	80021	80020	0	548339	0	0	80020	80020	0	0	210020	80011	10
80024	38879	80021	80021	80020	0	546309	0	0	80020	80020	0	0	210020	80011	10
80024	38904	80021	80021	80020	0	549018	0	0	80020	80020	0	0	210020	80011	10
80024	38945	80021	80021	80020	0	544927	0	0	80020	80020	0	0	210020	80011	10
80024	38898	80021	80021	80020	0	548589	0	0	80171	80171	0	0	210332	80130	10
80025	38932	80056	80056	80076	0	544645	0	0	80020	80020	0	0	210065	80017	10
80024	38900	80027	80027	80037	0	545183	0	0	80020	80020	0	0	210020	80011	10

CCMP (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations