Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (ST)

Test 1: uops

Code:

  dsb st

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)? int output thing (e9)? ldst retires (ed)
100416033100111000100040001000100011000
100416033100111000100040001000100011000
100416028100111000100040001000100011000
100416028100111000100040001000100011000
100416028100111000100040001000100011000
100416028100111000100040001000100011000
100416028100111000100040001000100011000
100416033100111000100040001000100011000
100416028100111000100040001000100011000
100416049101011009100040001000100011000

Test 2: throughput

Code:

  dsb st

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 16.0028

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
10204160033101051011000410010006300400241010620010006200001100000100
10204160033101071011000610010004300400161010420010004200001100000100
10204160028101051011000410010004300400161010420010004200001100000100
10204160028101051011000410010004300400161010420010004200001100000100
10204160028101051011000410010004300400161010420010004200001100000100
1020416002810105101100041001000430040016101042001000420000199990100
10204160028101051011000410010004300400161010420010004200001100000100
10204160028101051011000410010004300400161010420010004200001100000100
10204160028101051011000410010004300400161010420010004200001100000100
10204160028101051011000410010004300400161010420010004200001100000100

1000 unrolls and 10 iterations

Result (median cycles for code): 16.0028

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1002416003310015111000410100043040016010014201000402000110000010
1002416003310011111000010100003040000010010201000002000110000010
1002416002810011111000010100003040000010010201000002000110000010
1002416002810011111000010100003040000010010201000002000110000010
1002416002810011111000010100003040000010010201000002000110000010
100241600281001111100001010010304004001002020100100200019999010
1002416002810011111000010100003040000010010201000002000110000010
1002416002810011111000010100003040000010010201000002000110000010
1002416002810011111000010100003040000010010201000002000110000010
1002416002810011111000010100003040000010010201000002000110000010