Icestorm: SUBS (uxtx, 64-bit) measurements

Code:

  subs x0, x0, x1, uxtx

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  subs x0, x0, x1, uxtx

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10109	251598	10108	10210	20220	10001	10100
10205	10060	10115	10115	10148	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251641	10109	10210	20216	10001	10100
10204	10030	10101	10101	10108	251676	10109	10210	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	253201	10028	10028	20040	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253284	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010

Test 3: Latency 1->3

Code:

  subs x0, x1, x0, uxtx

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10109	251641	10106	10206	20212	10001	10100
10205	10060	10115	10115	10144	251647	10109	10210	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	253201	10028	10028	20020	10011	10010
10024	10030	10021	10021	10020	253239	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs x0, x1, x2, uxtx
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519339	20108	20216	30221	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs x0, x1, x2, uxtx
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519330	20107	20212	30218	20001	20100
20204	20030	20101	20101	20108	519434	20107	20214	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519956	20058	20084	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30116	20015	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010

Test 6: throughput

Count: 8

Code:

  subs x0, x8, x9, uxtx
  subs x1, x8, x9, uxtx
  subs x2, x8, x9, uxtx
  subs x3, x8, x9, uxtx
  subs x4, x8, x9, uxtx
  subs x5, x8, x9, uxtx
  subs x6, x8, x9, uxtx
  subs x7, x8, x9, uxtx

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5010

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	40096	80112	80112	80115	240448	80151	80252	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160298	80044	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	40080	80034	80034	80037	240067	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160118	80051	80010
80024	40036	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010

SUBS (uxtx, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations