Icestorm: STP (32-bit) measurements

Code:

  stp w0, w1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1153	1019	1	1018	1000	17007	1000	1000	3000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	3000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	3000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	3000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	3000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	3000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	3000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	3000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	3000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	3000	1	1000

Count: 8

Code:

  stp w0, w1, [x6]
  stp w0, w1, [x6]
  stp w0, w1, [x6]
  stp w0, w1, [x6]
  stp w0, w1, [x6]
  stp w0, w1, [x6]
  stp w0, w1, [x6]
  stp w0, w1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	80393	80119	101	80018	100	80001	300	1359938	80101	200	80008	200	240024	0	1	80000	0	100
80204	80045	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	0	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	0	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	0	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	0	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240147	0	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	0	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	0	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	0	1	80000	0	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	240024	0	1	80000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80152	80029	11	0	80018	10	0	80001	30	1360010	80011	20	80008	20	240000	1	80000	10
80024	80047	80011	11	0	80000	10	0	80000	30	1360043	80010	20	80000	20	240156	1	80000	10
80024	80047	80011	11	0	80000	10	0	80034	30	1360381	80044	20	80049	20	240000	1	80000	10
80024	80047	80011	11	0	80000	10	0	80000	30	1360043	80010	20	80000	20	240000	1	80000	10
80024	80047	80011	11	0	80000	10	0	80000	30	1360043	80010	20	80000	20	240000	1	80000	10
80024	80035	80011	11	0	80000	10	0	80003	30	1359968	80013	20	80010	20	240000	1	80000	10
80024	80045	80011	11	0	80000	10	0	80000	30	1360007	80010	20	80000	20	240000	1	80000	10
80024	80045	80011	11	0	80000	10	0	80000	30	1360007	80010	20	80000	20	240000	1	80000	10
80024	80045	80011	11	0	80000	10	0	80000	30	1360007	80010	20	80000	20	240000	1	80000	10
80024	80045	80011	11	0	80000	10	0	80000	30	1360007	80010	20	80000	20	240000	1	80000	10

STP (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations