Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SB

Test 1: uops

Code:

sb

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	? int output thing (e9)	? ldst retires (ed)
4004	22024	1001	1	1000	1000	4000	1000	1000	1	1000
4004	22024	1001	1	1000	1000	4000	1000	1000	1	1000
4004	22024	1001	1	1000	1000	4000	1000	1000	1	1000
4004	22024	1001	1	1000	1000	4000	1000	1000	1	1000
4004	22024	1001	1	1000	1000	4000	1000	1000	1	1000
4004	22024	1001	1	1000	1000	4000	1000	1000	1	1000
4004	22024	1001	1	1000	1000	4000	1000	1000	1	1000
4004	22024	1001	1	1000	1000	4000	1000	1000	1	1000
4004	22024	1001	1	1000	1000	4000	1000	1000	1	1000
4004	22024	1001	1	1000	1000	4000	1000	1000	1	1000

Test 2: throughput

Code:

sb

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 22.0432

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40204	220440	10102	101	0	10001	100	0	10001	300	40004	10101	200	10001	200	1	10000	100
40204	220432	10102	101	0	10001	100	0	10001	300	40004	10101	200	10001	200	1	10000	100
40205	220455	10103	101	0	10002	100	0	10001	300	40004	10101	200	10001	200	1	10000	100
40204	220432	10102	101	0	10001	100	0	10001	300	40004	10101	200	10001	200	1	10000	100
40204	220432	10102	101	0	10001	100	0	10001	300	40004	10101	200	10001	200	1	10000	100
40205	220455	10103	101	0	10002	100	0	10001	300	40004	10101	200	10001	200	1	10000	100
40204	220432	10102	101	0	10001	100	0	10001	300	40004	10101	200	10001	200	1	10000	100
40204	220448	10102	101	0	10001	100	0	10001	300	40004	10101	200	10001	200	1	10000	100
40204	220432	10102	101	0	10001	100	0	10001	300	40004	10101	200	10001	200	1	10000	100
40205	220455	10103	101	0	10002	100	0	10001	300	40004	10101	200	10001	200	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 22.0067

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
40025	220103	10013	11	10002	10	10001	30	40004	10011	20	10001	20	0	1	10000	0	10
40024	220067	10011	11	10000	10	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
40024	220067	10011	11	10000	10	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
40024	220067	10011	11	10000	10	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
40024	220067	10011	11	10000	10	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
40024	220067	10011	11	10000	10	10002	30	40008	10012	20	10002	20	0	1	10000	0	10
40024	220067	10011	11	10000	10	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
40024	220067	10011	11	10000	10	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
40024	220067	10011	11	10000	10	10003	30	40012	10013	20	10003	20	0	1	10000	0	10
40024	220067	10011	11	10000	10	10002	30	40008	10012	20	10002	20	0	1	10000	0	10