Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SB

Test 1: uops

Code:

  sb

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)? int output thing (e9)? ldst retires (ed)
400422024100111000100040001000100011000
400422024100111000100040001000100011000
400422024100111000100040001000100011000
400422024100111000100040001000100011000
400422024100111000100040001000100011000
400422024100111000100040001000100011000
400422024100111000100040001000100011000
400422024100111000100040001000100011000
400422024100111000100040001000100011000
400422024100111000100040001000100011000

Test 2: throughput

Code:

  sb

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 22.0432

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020422044010102101010001100010001300400041010120010001200110000100
4020422043210102101010001100010001300400041010120010001200110000100
4020522045510103101010002100010001300400041010120010001200110000100
4020422043210102101010001100010001300400041010120010001200110000100
4020422043210102101010001100010001300400041010120010001200110000100
4020522045510103101010002100010001300400041010120010001200110000100
4020422043210102101010001100010001300400041010120010001200110000100
4020422044810102101010001100010001300400041010120010001200110000100
4020422043210102101010001100010001300400041010120010001200110000100
4020522045510103101010002100010001300400041010120010001200110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 22.0067

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4002522010310013111000210100013040004100112010001200110000010
4002422006710011111000010100003040000100102010000200110000010
4002422006710011111000010100003040000100102010000200110000010
4002422006710011111000010100003040000100102010000200110000010
4002422006710011111000010100003040000100102010000200110000010
4002422006710011111000010100023040008100122010002200110000010
4002422006710011111000010100003040000100102010000200110000010
4002422006710011111000010100003040000100102010000200110000010
4002422006710011111000010100033040012100132010003200110000010
4002422006710011111000010100023040008100122010002200110000010