Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PSTL2STRM)

Test 1: uops

Code:

  prfm pstl2strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2086	1001	1	1000	1000	34742	1000	1000	1000	1	1000
1004	2105	1001	1	1000	1048	35659	1048	1057	1000	1	1000
1004	2097	1001	1	1000	1000	34918	1000	1000	1000	1	1000
1004	2101	1001	1	1000	1000	34894	1000	1000	1000	1	1000
1004	2111	1001	1	1000	1000	34858	1000	1000	1000	1	1000
1004	2084	1001	1	1000	1000	34740	1000	1000	1000	1	1000
1004	2074	1001	1	1000	1000	35000	1000	1000	1000	1	1000
1004	2099	1001	1	1000	1000	34896	1000	1000	1000	1	1000
1004	2099	1001	1	1000	1000	34940	1000	1000	1000	1	1000
1004	2074	1001	1	1000	1000	34960	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm pstl2strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0120

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	20778	20101	10101	10000	10102	10000	61370	349215	20101	10203	10003	10203	10003	10001	10000	10100
20204	20049	20101	10101	10000	10102	10000	61323	349215	20102	10204	10004	10204	10004	10001	10000	10100
20204	20049	20101	10101	10000	10102	10000	61323	349215	20102	10204	10004	10204	10004	10001	10000	10100
20204	20049	20101	10101	10000	10102	10000	61323	349215	20102	10204	10004	10204	10004	10001	10000	10100
20204	20049	20101	10101	10000	10102	10000	61323	349215	20102	10204	10004	10204	10004	10001	10000	10100
20204	20049	20101	10101	10000	10102	10000	61323	349215	20102	10204	10004	10204	10004	10001	10000	10100
20204	20049	20101	10101	10000	10102	10000	61323	349215	20102	10204	10004	10234	10034	10032	10000	10100
20204	20049	20101	10101	10000	10102	10004	61203	350363	20114	10212	10012	10204	10004	10001	10000	10100
20204	20078	20101	10101	10000	10102	10000	61323	349215	20102	10204	10004	10204	10004	10001	10000	10100
20204	20049	20101	10101	10000	10102	10000	61323	349215	20102	10204	10004	10204	10004	10001	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0122

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	20849	20014	10014	10000	10013	10000	61056	350575	20014	10026	10006	10020	10000	10001	10000	10010
20024	20122	20011	10011	10000	10010	10000	61032	350575	20010	10020	10000	10020	10000	10001	10000	10010
20024	20122	20011	10011	10000	10010	10000	61032	350575	20010	10020	10000	10020	10000	10001	10000	10010
20024	20122	20011	10011	10000	10010	10000	61032	350575	20010	10020	10000	10020	10000	10001	10000	10010
20024	20122	20011	10011	10000	10010	10000	61032	350575	20010	10020	10000	10020	10000	10001	10000	10010
20024	20122	20011	10011	10000	10010	10000	61032	350575	20010	10020	10000	10020	10000	10001	10000	10010
20024	20122	20011	10011	10000	10010	10000	61032	350575	20010	10020	10000	10020	10000	10001	10000	10010
20024	20122	20011	10011	10000	10010	10000	61032	350575	20010	10020	10000	10020	10000	10001	10000	10010
20024	20122	20011	10011	10000	10010	10000	61032	350575	20010	10020	10000	10020	10000	10001	10000	10010
20024	20122	20011	10011	10000	10010	10000	61032	350575	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm pstl2strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.8718

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	19154	10101	101	10000	100	10000	300	332006	10100	200	10010	200	10012	1	10000	100
10204	18718	10101	101	10000	100	10006	300	325270	10106	200	10012	200	10012	1	10000	100
10204	18718	10101	101	10000	100	10006	300	325270	10106	200	10012	200	10012	1	10000	100
10204	18718	10101	101	10000	100	10006	300	325270	10106	200	10012	200	10012	1	10000	100
10204	18946	10101	101	10000	100	10006	300	325270	10106	200	10012	200	10012	1	10000	100
10204	19291	10101	101	10000	100	10000	300	335988	10100	200	10008	200	10004	1	10000	100
10204	19376	10101	101	10000	100	10002	300	338922	10102	200	10012	200	10008	1	10000	100
10204	18998	10101	101	10000	100	10004	300	337398	10104	200	10012	200	10004	1	10000	100
10204	19186	10101	101	10000	100	10004	300	335434	10104	200	10012	200	10008	1	10000	100
10204	19234	10101	101	10000	100	10004	300	335466	10104	200	10012	200	10012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0048

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	20039	10011	11	10000	10	10006	30	349222	10016	20	10012	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20074	10011	11	10000	10	10000	30	349292	10010	20	10000	20	10000	1	10000	10
10024	20090	10011	11	10000	10	10000	30	349618	10010	20	10000	20	10000	1	10000	10
10024	20050	10011	11	10000	10	10000	30	349972	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349434	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10