Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
sbcs w0, w0, w1
mov x0, 1 mov x1, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 1.001
Load/store unit issues: 0.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
1004 | 1030 | 1001 | 1001 | 1000 | 25043 | 1000 | 1000 | 3000 | 1001 | 1000 |
1004 | 1030 | 1001 | 1001 | 1000 | 25043 | 1000 | 1000 | 3000 | 1001 | 1000 |
1004 | 1030 | 1001 | 1001 | 1000 | 25043 | 1000 | 1000 | 3000 | 1001 | 1000 |
1004 | 1030 | 1001 | 1001 | 1000 | 25043 | 1000 | 1000 | 3000 | 1001 | 1000 |
1004 | 1030 | 1001 | 1001 | 1000 | 25043 | 1000 | 1000 | 3000 | 1001 | 1000 |
1004 | 1030 | 1001 | 1001 | 1000 | 25043 | 1000 | 1000 | 3000 | 1001 | 1000 |
1004 | 1030 | 1001 | 1001 | 1000 | 25043 | 1000 | 1000 | 3000 | 1001 | 1000 |
1004 | 1030 | 1001 | 1001 | 1000 | 25043 | 1000 | 1000 | 3000 | 1001 | 1000 |
1004 | 1030 | 1001 | 1001 | 1000 | 25043 | 1000 | 1000 | 3000 | 1001 | 1000 |
1004 | 1030 | 1001 | 1001 | 1000 | 25043 | 1000 | 1000 | 3000 | 1001 | 1000 |
Code:
sbcs w0, w0, w1
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
10204 | 10030 | 10101 | 10101 | 10107 | 251598 | 10108 | 10210 | 30218 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30230 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
Result (median cycles for code): 1.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
10024 | 10030 | 10021 | 10021 | 10028 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
Code:
sbcs w0, w1, w0
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
10204 | 10030 | 10101 | 10101 | 10108 | 251520 | 10106 | 10206 | 30230 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
10204 | 10030 | 10101 | 10101 | 10108 | 251774 | 10108 | 10208 | 30224 | 10001 | 10100 |
Result (median cycles for code): 1.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
10024 | 10030 | 10021 | 10021 | 10030 | 253292 | 10028 | 10030 | 30050 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253239 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253161 | 10020 | 10020 | 30020 | 10011 | 10010 |
Chain cycles: 1
Code:
sbcs w0, w1, w2 tst x0, 1
mov x0, 1 mov x1, 2 mov x2, 3
(non-fused SUB/CBNZ loop)
Result (median cycles for code, minus 1 chain cycle): 1.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
20204 | 20030 | 20201 | 20201 | 20208 | 508745 | 20208 | 20208 | 40216 | 20101 | 10100 |
20204 | 20030 | 20201 | 20201 | 20208 | 509018 | 20208 | 20208 | 40216 | 20101 | 10100 |
20205 | 20060 | 20215 | 20215 | 20245 | 508839 | 20208 | 20208 | 40216 | 20101 | 10100 |
20204 | 20030 | 20201 | 20201 | 20208 | 509018 | 20208 | 20208 | 40216 | 20101 | 10100 |
20204 | 20030 | 20201 | 20201 | 20208 | 509018 | 20208 | 20208 | 40216 | 20101 | 10100 |
20204 | 20030 | 20201 | 20201 | 20208 | 509018 | 20208 | 20208 | 40216 | 20101 | 10100 |
20204 | 20030 | 20201 | 20201 | 20208 | 509018 | 20208 | 20208 | 40216 | 20101 | 10100 |
20204 | 20030 | 20201 | 20201 | 20208 | 509018 | 20208 | 20208 | 40216 | 20101 | 10100 |
20204 | 20030 | 20201 | 20201 | 20208 | 509018 | 20208 | 20208 | 40216 | 20101 | 10100 |
20204 | 20030 | 20201 | 20201 | 20208 | 509018 | 20208 | 20208 | 40216 | 20101 | 10100 |
Result (median cycles for code, minus 1 chain cycle): 1.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
20024 | 20030 | 20021 | 20021 | 20031 | 509705 | 20020 | 20020 | 40020 | 20011 | 10010 |
20024 | 20030 | 20021 | 20021 | 20020 | 509904 | 20020 | 20020 | 40020 | 20011 | 10010 |
20024 | 20030 | 20021 | 20021 | 20020 | 509904 | 20020 | 20020 | 40020 | 20011 | 10010 |
20024 | 20030 | 20021 | 20021 | 20020 | 510324 | 20069 | 20072 | 40020 | 20011 | 10010 |
20024 | 20030 | 20021 | 20021 | 20020 | 509904 | 20020 | 20020 | 40020 | 20011 | 10010 |
20024 | 20030 | 20021 | 20021 | 20020 | 509904 | 20020 | 20020 | 40020 | 20011 | 10010 |
20024 | 20030 | 20021 | 20021 | 20020 | 509904 | 20020 | 20020 | 40020 | 20011 | 10010 |
20024 | 20030 | 20021 | 20021 | 20020 | 509904 | 20020 | 20020 | 40020 | 20011 | 10010 |
20024 | 20030 | 20021 | 20021 | 20020 | 509904 | 20020 | 20020 | 40020 | 20011 | 10010 |
20024 | 20030 | 20021 | 20021 | 20020 | 509904 | 20020 | 20020 | 40020 | 20011 | 10010 |
Chain cycles: 1
Code:
sbcs w0, w1, w2 cset x1, cc
mov x0, 1 mov x1, 2 mov x2, 3 mov x3, 4 mov x4, 5
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 1 chain cycle): 1.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
20204 | 20030 | 20101 | 20101 | 20107 | 519320 | 20108 | 20214 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
Result (median cycles for code, minus 1 chain cycle): 1.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
20024 | 20030 | 20011 | 20011 | 20018 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
Chain cycles: 1
Code:
sbcs w0, w1, w2 cset x2, cc
mov x0, 1 mov x1, 2 mov x2, 3 mov x3, 4 mov x4, 5
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 1 chain cycle): 1.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
20204 | 20030 | 20101 | 20101 | 20108 | 519234 | 20108 | 20216 | 40224 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20107 | 519434 | 20107 | 20214 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20205 | 20060 | 20115 | 20115 | 20147 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
20204 | 20030 | 20101 | 20101 | 20108 | 519548 | 20108 | 20216 | 40232 | 20001 | 20100 |
Result (median cycles for code, minus 1 chain cycle): 1.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
20024 | 20030 | 20011 | 20011 | 20018 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
20024 | 20030 | 20011 | 20011 | 20010 | 519598 | 20010 | 20020 | 40020 | 20001 | 20010 |
Code:
sbcs w0, w1, w2
mov x0, 1 mov x1, 2 mov x2, 3 mov x3, 4 mov x4, 5
(non-fused SUB/CBNZ loop)
Result (median cycles for code): 1.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
10204 | 10030 | 10201 | 10201 | 10208 | 253037 | 10208 | 10208 | 30230 | 10101 | 10100 |
10204 | 10030 | 10201 | 10201 | 10208 | 253318 | 10210 | 10210 | 30224 | 10101 | 10100 |
10204 | 10030 | 10201 | 10201 | 10208 | 253432 | 10208 | 10208 | 30224 | 10101 | 10100 |
10204 | 10030 | 10201 | 10201 | 10208 | 253432 | 10208 | 10208 | 30224 | 10101 | 10100 |
10204 | 10030 | 10201 | 10201 | 10208 | 253432 | 10208 | 10208 | 30224 | 10101 | 10100 |
10204 | 10030 | 10201 | 10201 | 10208 | 253432 | 10208 | 10208 | 30338 | 10115 | 10100 |
10204 | 10030 | 10201 | 10201 | 10208 | 253432 | 10208 | 10208 | 30224 | 10101 | 10100 |
10204 | 10030 | 10201 | 10201 | 10208 | 253432 | 10208 | 10208 | 30224 | 10101 | 10100 |
10204 | 10030 | 10201 | 10201 | 10208 | 253432 | 10208 | 10208 | 30224 | 10101 | 10100 |
10204 | 10030 | 10201 | 10201 | 10208 | 253432 | 10208 | 10208 | 30224 | 10101 | 10100 |
Result (median cycles for code): 1.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
10024 | 10030 | 10021 | 10021 | 10029 | 253114 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253383 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253383 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253383 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253383 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253383 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253383 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253878 | 10067 | 10067 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253383 | 10020 | 10020 | 30020 | 10011 | 10010 |
10024 | 10030 | 10021 | 10021 | 10020 | 253383 | 10020 | 10020 | 30020 | 10011 | 10010 |
Count: 8
Code:
ands xzr, xzr, xzr sbcs w0, w8, w9 ands xzr, xzr, xzr sbcs w1, w8, w9 ands xzr, xzr, xzr sbcs w2, w8, w9 ands xzr, xzr, xzr sbcs w3, w8, w9 ands xzr, xzr, xzr sbcs w4, w8, w9 ands xzr, xzr, xzr sbcs w5, w8, w9 ands xzr, xzr, xzr sbcs w6, w8, w9 ands xzr, xzr, xzr sbcs w7, w8, w9
mov x8, 9 mov x9, 10 mov x10, 11
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.7992
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
160204 | 64019 | 160115 | 160115 | 160122 | 682218 | 160119 | 160220 | 240224 | 160012 | 80100 |
160204 | 63943 | 160111 | 160111 | 160115 | 681993 | 160116 | 160216 | 240230 | 160011 | 80100 |
160204 | 63935 | 160115 | 160115 | 160119 | 682244 | 160119 | 160220 | 240230 | 160015 | 80100 |
160204 | 63912 | 160113 | 160113 | 160119 | 682001 | 160119 | 160220 | 240224 | 160012 | 80100 |
160204 | 63936 | 160111 | 160111 | 160115 | 682227 | 160115 | 160216 | 240230 | 160013 | 80100 |
160204 | 63915 | 160113 | 160113 | 160119 | 682179 | 160118 | 160220 | 240224 | 160012 | 80100 |
160204 | 63920 | 160110 | 160110 | 160115 | 682244 | 160119 | 160220 | 240230 | 160015 | 80100 |
160204 | 63899 | 160110 | 160110 | 160115 | 682082 | 160155 | 160255 | 240224 | 160011 | 80100 |
160204 | 63933 | 160115 | 160115 | 160119 | 682244 | 160119 | 160220 | 240224 | 160011 | 80100 |
160204 | 63928 | 160111 | 160111 | 160115 | 682101 | 160118 | 160220 | 240230 | 160015 | 80100 |
Result (median cycles for code divided by count): 0.7985
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
160024 | 65337 | 160011 | 160011 | 160010 | 681990 | 160010 | 160020 | 240020 | 160001 | 80010 |
160024 | 64150 | 160011 | 160011 | 160010 | 682417 | 160010 | 160020 | 240020 | 160001 | 80010 |
160024 | 63905 | 160011 | 160011 | 160010 | 682380 | 160010 | 160020 | 240020 | 160001 | 80010 |
160024 | 63880 | 160011 | 160011 | 160010 | 682463 | 160010 | 160020 | 240116 | 160055 | 80010 |
160024 | 63894 | 160011 | 160011 | 160010 | 682812 | 160010 | 160020 | 240020 | 160001 | 80010 |
160024 | 63909 | 160011 | 160011 | 160010 | 682437 | 160010 | 160020 | 240020 | 160001 | 80010 |
160024 | 63885 | 160011 | 160011 | 160010 | 682419 | 160010 | 160020 | 240020 | 160001 | 80010 |
160024 | 63902 | 160011 | 160011 | 160010 | 682745 | 160010 | 160020 | 240020 | 160001 | 80010 |
160024 | 63894 | 160011 | 160011 | 160010 | 682768 | 160010 | 160020 | 240020 | 160001 | 80010 |
160024 | 63909 | 160011 | 160011 | 160010 | 682584 | 160010 | 160020 | 240020 | 160001 | 80010 |
Count: 4
Code:
fcmp s0, s0 sbcs w0, w4, w5 sbcs w1, w4, w5 sbcs w2, w4, w5 sbcs w3, w4, w5
mov x4, 5 mov x5, 6 mov x6, 7
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.6208
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? int retires (ef) |
50204 | 24846 | 50105 | 40103 | 10002 | 0 | 40111 | 10003 | 309222 | 40017 | 50116 | 40212 | 10004 | 120236 | 20008 | 40002 | 40100 |
50204 | 24831 | 50104 | 40101 | 10003 | 0 | 40112 | 10004 | 308941 | 40017 | 50116 | 40212 | 10004 | 120236 | 20008 | 40001 | 40100 |
50204 | 24831 | 50104 | 40101 | 10003 | 0 | 40112 | 10004 | 309222 | 40017 | 50116 | 40212 | 10004 | 120236 | 20008 | 40001 | 40100 |
50204 | 24831 | 50104 | 40101 | 10003 | 0 | 40112 | 10004 | 309224 | 40017 | 50116 | 40212 | 10004 | 120236 | 20008 | 40001 | 40100 |
50204 | 24831 | 50104 | 40101 | 10003 | 0 | 40112 | 10004 | 309224 | 40017 | 50116 | 40212 | 10004 | 120236 | 20008 | 40001 | 40100 |
50204 | 24831 | 50104 | 40101 | 10003 | 0 | 40112 | 10004 | 309224 | 40017 | 50116 | 40212 | 10004 | 120236 | 20008 | 40001 | 40100 |
50204 | 24831 | 50104 | 40101 | 10003 | 0 | 40112 | 10004 | 309224 | 40017 | 50116 | 40212 | 10004 | 120236 | 20008 | 40001 | 40100 |
50204 | 24831 | 50104 | 40101 | 10003 | 0 | 40112 | 10004 | 309222 | 40017 | 50116 | 40212 | 10004 | 120236 | 20008 | 40001 | 40100 |
50204 | 24831 | 50104 | 40101 | 10003 | 0 | 40112 | 10004 | 309224 | 40017 | 50116 | 40212 | 10004 | 120236 | 20008 | 40001 | 40100 |
50204 | 24831 | 50104 | 40101 | 10003 | 0 | 40112 | 10004 | 309224 | 40017 | 50116 | 40212 | 10004 | 120236 | 20008 | 40001 | 40100 |
Result (median cycles for code divided by count): 0.6197
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? int retires (ef) |
50024 | 24872 | 50016 | 40014 | 10002 | 40024 | 10004 | 312100 | 40013 | 50022 | 40029 | 10003 | 120020 | 20000 | 40001 | 40010 |
50024 | 24783 | 50011 | 40011 | 10000 | 40010 | 10000 | 311978 | 40000 | 50010 | 40020 | 10000 | 120020 | 20000 | 40001 | 40010 |
50024 | 24789 | 50011 | 40011 | 10000 | 40010 | 10000 | 311978 | 40000 | 50010 | 40020 | 10000 | 120020 | 20000 | 40001 | 40010 |
50024 | 24789 | 50011 | 40011 | 10000 | 40010 | 10000 | 311976 | 40000 | 50010 | 40020 | 10000 | 120020 | 20000 | 40001 | 40010 |
50024 | 24789 | 50011 | 40011 | 10000 | 40010 | 10000 | 311976 | 40000 | 50010 | 40020 | 10000 | 120020 | 20000 | 40001 | 40010 |
50024 | 24783 | 50011 | 40011 | 10000 | 40010 | 10000 | 311978 | 40000 | 50010 | 40020 | 10000 | 120020 | 20000 | 40001 | 40010 |
50024 | 24789 | 50011 | 40011 | 10000 | 40010 | 10000 | 311978 | 40000 | 50010 | 40020 | 10000 | 120020 | 20000 | 40001 | 40010 |
50024 | 24789 | 50011 | 40011 | 10000 | 40010 | 10000 | 311976 | 40000 | 50010 | 40020 | 10000 | 120020 | 20000 | 40001 | 40010 |
50024 | 24789 | 50011 | 40011 | 10000 | 40010 | 10000 | 311976 | 40000 | 50010 | 40020 | 10000 | 120020 | 20000 | 40001 | 40010 |
50024 | 24789 | 50011 | 40011 | 10000 | 40010 | 10000 | 311976 | 40000 | 50010 | 40020 | 10000 | 120020 | 20000 | 40001 | 40010 |
Count: 7
Code:
ands xzr, xzr, xzr sbcs w0, w7, w8 sbcs w1, w7, w8 sbcs w2, w7, w8 sbcs w3, w7, w8 sbcs w4, w7, w8 sbcs w5, w7, w8 sbcs w6, w7, w8
mov x7, 8 mov x8, 9 mov x9, 10
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5844
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
80204 | 40924 | 80110 | 80110 | 80117 | 541532 | 80112 | 80212 | 210230 | 80007 | 70100 |
80204 | 40905 | 80107 | 80107 | 80112 | 537008 | 80151 | 80251 | 210242 | 80011 | 70100 |
80204 | 40905 | 80107 | 80107 | 80112 | 541028 | 80112 | 80212 | 210230 | 80007 | 70100 |
80204 | 40905 | 80107 | 80107 | 80112 | 541028 | 80112 | 80212 | 210230 | 80007 | 70100 |
80204 | 40905 | 80107 | 80107 | 80112 | 541028 | 80112 | 80212 | 210230 | 80007 | 70100 |
80204 | 40905 | 80107 | 80107 | 80112 | 541028 | 80112 | 80212 | 210230 | 80007 | 70100 |
80204 | 40905 | 80107 | 80107 | 80112 | 541028 | 80112 | 80212 | 210230 | 80007 | 70100 |
80204 | 40905 | 80107 | 80107 | 80112 | 541028 | 80112 | 80212 | 210230 | 80007 | 70100 |
80204 | 40905 | 80107 | 80107 | 80112 | 541028 | 80112 | 80212 | 210230 | 80007 | 70100 |
80204 | 40905 | 80107 | 80107 | 80112 | 540465 | 80112 | 80212 | 210230 | 80007 | 70100 |
Result (median cycles for code divided by count): 0.5839
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
80024 | 41285 | 80181 | 80181 | 80189 | 540922 | 80036 | 80036 | 210020 | 80011 | 70010 |
80024 | 40876 | 80021 | 80021 | 80020 | 542624 | 80020 | 80020 | 210020 | 80011 | 70010 |
80024 | 40876 | 80021 | 80021 | 80020 | 542624 | 80020 | 80020 | 210020 | 80011 | 70010 |
80024 | 40876 | 80021 | 80021 | 80020 | 542624 | 80020 | 80020 | 210020 | 80011 | 70010 |
80024 | 40876 | 80021 | 80021 | 80020 | 542624 | 80020 | 80020 | 210224 | 80088 | 70010 |
80024 | 40876 | 80021 | 80021 | 80020 | 542624 | 80020 | 80020 | 210020 | 80011 | 70010 |
80024 | 40876 | 80021 | 80021 | 80020 | 542624 | 80020 | 80020 | 210020 | 80011 | 70010 |
80024 | 40876 | 80021 | 80021 | 80020 | 542624 | 80020 | 80020 | 210170 | 80046 | 70010 |
80024 | 40876 | 80021 | 80021 | 80020 | 542624 | 80020 | 80020 | 210020 | 80011 | 70010 |
80024 | 40876 | 80021 | 80021 | 80020 | 542624 | 80020 | 80020 | 210167 | 80049 | 70010 |