Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SBCS (32-bit)

Test 1: uops

Code:

  sbcs w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100410301001100110002504310001000300010011000
100410301001100110002504310001000300010011000
100410301001100110002504310001000300010011000
100410301001100110002504310001000300010011000
100410301001100110002504310001000300010011000
100410301001100110002504310001000300010011000
100410301001100110002504310001000300010011000
100410301001100110002504310001000300010011000
100410301001100110002504310001000300010011000
100410301001100110002504310001000300010011000

Test 2: Latency 1->2

Code:

  sbcs w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101072515981010810210302181000110100
10204100301010110101101082517741010810208302301000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010

Test 3: Latency 1->3

Code:

  sbcs w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101082515201010610206302301000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100
10204100301010110101101082517741010810208302241000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100302532921002810030300501001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202532391002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010
10024100301002110021100202531611002010020300201001110010

Test 4: Latency 1->4

Chain cycles: 1

Code:

  sbcs w0, w1, w2
  tst x0, 1
  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204200302020120201202085087452020820208402162010110100
20204200302020120201202085090182020820208402162010110100
20205200602021520215202455088392020820208402162010110100
20204200302020120201202085090182020820208402162010110100
20204200302020120201202085090182020820208402162010110100
20204200302020120201202085090182020820208402162010110100
20204200302020120201202085090182020820208402162010110100
20204200302020120201202085090182020820208402162010110100
20204200302020120201202085090182020820208402162010110100
20204200302020120201202085090182020820208402162010110100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024200302002120021200315097052002020020400202001110010
20024200302002120021200205099042002020020400202001110010
20024200302002120021200205099042002020020400202001110010
20024200302002120021200205103242006920072400202001110010
20024200302002120021200205099042002020020400202001110010
20024200302002120021200205099042002020020400202001110010
20024200302002120021200205099042002020020400202001110010
20024200302002120021200205099042002020020400202001110010
20024200302002120021200205099042002020020400202001110010
20024200302002120021200205099042002020020400202001110010

Test 5: Latency 4->2

Chain cycles: 1

Code:

  sbcs w0, w1, w2
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204200302010120101201075193202010820214402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024200302001120011200185195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010

Test 6: Latency 4->3

Chain cycles: 1

Code:

  sbcs w0, w1, w2
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204200302010120101201085192342010820216402242000120100
20204200302010120101201075194342010720214402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100
20205200602011520115201475195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100
20204200302010120101201085195482010820216402322000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024200302001120011200185195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010
20024200302001120011200105195982001020020400202000120010

Test 7: Latency 4->4

Code:

  sbcs w0, w1, w2
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301020110201102082530371020810208302301010110100
10204100301020110201102082533181021010210302241010110100
10204100301020110201102082534321020810208302241010110100
10204100301020110201102082534321020810208302241010110100
10204100301020110201102082534321020810208302241010110100
10204100301020110201102082534321020810208303381011510100
10204100301020110201102082534321020810208302241010110100
10204100301020110201102082534321020810208302241010110100
10204100301020110201102082534321020810208302241010110100
10204100301020110201102082534321020810208302241010110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100292531141002010020300201001110010
10024100301002110021100202533831002010020300201001110010
10024100301002110021100202533831002010020300201001110010
10024100301002110021100202533831002010020300201001110010
10024100301002110021100202533831002010020300201001110010
10024100301002110021100202533831002010020300201001110010
10024100301002110021100202533831002010020300201001110010
10024100301002110021100202538781006710067300201001110010
10024100301002110021100202533831002010020300201001110010
10024100301002110021100202533831002010020300201001110010

Test 8: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  sbcs w0, w8, w9
  ands xzr, xzr, xzr
  sbcs w1, w8, w9
  ands xzr, xzr, xzr
  sbcs w2, w8, w9
  ands xzr, xzr, xzr
  sbcs w3, w8, w9
  ands xzr, xzr, xzr
  sbcs w4, w8, w9
  ands xzr, xzr, xzr
  sbcs w5, w8, w9
  ands xzr, xzr, xzr
  sbcs w6, w8, w9
  ands xzr, xzr, xzr
  sbcs w7, w8, w9
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7992

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
1602046401916011516011516012268221816011916022024022416001280100
1602046394316011116011116011568199316011616021624023016001180100
1602046393516011516011516011968224416011916022024023016001580100
1602046391216011316011316011968200116011916022024022416001280100
1602046393616011116011116011568222716011516021624023016001380100
1602046391516011316011316011968217916011816022024022416001280100
1602046392016011016011016011568224416011916022024023016001580100
1602046389916011016011016011568208216015516025524022416001180100
1602046393316011516011516011968224416011916022024022416001180100
1602046392816011116011116011568210116011816022024023016001580100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7985

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
1600246533716001116001116001068199016001016002024002016000180010
1600246415016001116001116001068241716001016002024002016000180010
1600246390516001116001116001068238016001016002024002016000180010
1600246388016001116001116001068246316001016002024011616005580010
1600246389416001116001116001068281216001016002024002016000180010
1600246390916001116001116001068243716001016002024002016000180010
1600246388516001116001116001068241916001016002024002016000180010
1600246390216001116001116001068274516001016002024002016000180010
1600246389416001116001116001068276816001016002024002016000180010
1600246390916001116001116001068258416001016002024002016000180010

Test 9: throughput

Count: 4

Code:

  fcmp s0, s0
  sbcs w0, w4, w5
  sbcs w1, w4, w5
  sbcs w2, w4, w5
  sbcs w3, w4, w5
  mov x4, 5
  mov x5, 6
  mov x6, 7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6208

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? int retires (ef)
50204248465010540103100020401111000330922240017501164021210004120236200084000240100
50204248315010440101100030401121000430894140017501164021210004120236200084000140100
50204248315010440101100030401121000430922240017501164021210004120236200084000140100
50204248315010440101100030401121000430922440017501164021210004120236200084000140100
50204248315010440101100030401121000430922440017501164021210004120236200084000140100
50204248315010440101100030401121000430922440017501164021210004120236200084000140100
50204248315010440101100030401121000430922440017501164021210004120236200084000140100
50204248315010440101100030401121000430922240017501164021210004120236200084000140100
50204248315010440101100030401121000430922440017501164021210004120236200084000140100
50204248315010440101100030401121000430922440017501164021210004120236200084000140100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6197

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? int retires (ef)
5002424872500164001410002400241000431210040013500224002910003120020200004000140010
5002424783500114001110000400101000031197840000500104002010000120020200004000140010
5002424789500114001110000400101000031197840000500104002010000120020200004000140010
5002424789500114001110000400101000031197640000500104002010000120020200004000140010
5002424789500114001110000400101000031197640000500104002010000120020200004000140010
5002424783500114001110000400101000031197840000500104002010000120020200004000140010
5002424789500114001110000400101000031197840000500104002010000120020200004000140010
5002424789500114001110000400101000031197640000500104002010000120020200004000140010
5002424789500114001110000400101000031197640000500104002010000120020200004000140010
5002424789500114001110000400101000031197640000500104002010000120020200004000140010

Test 10: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  sbcs w0, w7, w8
  sbcs w1, w7, w8
  sbcs w2, w7, w8
  sbcs w3, w7, w8
  sbcs w4, w7, w8
  sbcs w5, w7, w8
  sbcs w6, w7, w8
  mov x7, 8
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5844

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802044092480110801108011754153280112802122102308000770100
802044090580107801078011253700880151802512102428001170100
802044090580107801078011254102880112802122102308000770100
802044090580107801078011254102880112802122102308000770100
802044090580107801078011254102880112802122102308000770100
802044090580107801078011254102880112802122102308000770100
802044090580107801078011254102880112802122102308000770100
802044090580107801078011254102880112802122102308000770100
802044090580107801078011254102880112802122102308000770100
802044090580107801078011254046580112802122102308000770100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5839

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800244128580181801818018954092280036800362100208001170010
800244087680021800218002054262480020800202100208001170010
800244087680021800218002054262480020800202100208001170010
800244087680021800218002054262480020800202100208001170010
800244087680021800218002054262480020800202102248008870010
800244087680021800218002054262480020800202100208001170010
800244087680021800218002054262480020800202100208001170010
800244087680021800218002054262480020800202101708004670010
800244087680021800218002054262480020800202100208001170010
800244087680021800218002054262480020800202101678004970010