Icestorm: STP (post-index, 32-bit) measurements

Code:

  stp w0, w1, [x6], #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1640	2059	1041	1018	1040	1000	4761	17497	2000	1000	3000	1001	1000
1004	1102	2001	1001	1000	1000	1000	4761	17479	2000	1000	3000	1001	1000
1004	1066	2001	1001	1000	1000	1000	4761	17497	2000	1000	3000	1001	1000
1004	1065	2001	1001	1000	1000	1000	4761	17407	2000	1000	3000	1001	1000
1004	1075	2001	1001	1000	1000	1000	4801	17461	2000	1000	3000	1001	1000
1004	1074	2001	1001	1000	1000	1000	4761	18091	2000	1000	3000	1001	1000
1004	1065	2001	1001	1000	1000	1000	4761	17569	2000	1000	3000	1001	1000
1004	1068	2001	1001	1000	1000	1000	4761	17569	2000	1000	3000	1001	1000
1004	1068	2001	1001	1000	1000	1000	4761	17821	2000	1000	3000	1001	1000
1004	1068	2001	1001	1000	1000	1000	4761	18037	2000	1000	3000	1001	1000

Test 2: Latency 3->3

Code:

  stp w0, w1, [x6], #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0107

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10209	11211	20400	10310	10090	10310	10003	68367	171009	20109	200	10010	200	30030	10005	10000	100
10204	10105	20105	10105	10000	10106	10002	43550	171169	20106	200	10008	200	30024	10004	10000	100
10204	10106	20104	10104	10000	10104	10002	43550	171151	20106	200	10008	200	30024	10004	10000	100
10205	10195	20155	10138	10017	10143	10002	43536	171641	20106	200	10008	200	30024	10004	10000	100
10204	10121	20104	10104	10000	10104	10002	43554	171475	20106	200	10008	200	30024	10004	10000	100
10204	10108	20104	10104	10000	10104	10002	43550	171187	20106	200	10008	200	30024	10004	10000	100
10204	10107	20104	10104	10000	10104	10002	43550	171151	20106	200	10008	200	30024	10004	10000	100
10204	10107	20104	10104	10000	10104	10002	43550	171151	20106	200	10008	200	30024	10004	10000	100
10204	10107	20104	10104	10000	10104	10002	43550	171169	20106	200	10008	200	30024	10004	10000	100
10204	10107	20104	10104	10000	10104	10002	43550	171151	20106	200	10008	200	30024	10004	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0090

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10029	11556	20304	10214	10090	10214	10002	101257	170760	20016	20	10008	20	30030	10002	10000	10
10024	10102	20014	10014	10000	10014	10000	43091	171235	20010	20	10000	20	30000	10001	10000	10
10024	10110	20011	10011	10000	10010	10000	43095	171577	20010	20	10000	20	30000	10001	10000	10
10024	10118	20011	10011	10000	10010	10000	43092	171163	20010	20	10000	20	30000	10001	10000	10
10024	10101	20011	10011	10000	10010	10000	43087	171145	20010	20	10000	20	30000	10001	10000	10
10024	10101	20011	10011	10000	10010	10000	43092	170875	20010	20	10000	20	30000	10001	10000	10
10024	10101	20011	10011	10000	10010	10000	43093	171019	20010	20	10000	20	30000	10001	10000	10
10024	10102	20011	10011	10000	10010	10000	43092	171217	20010	20	10000	20	30000	10001	10000	10
10024	10081	20011	10011	10000	10010	10000	43099	170677	20010	20	10000	20	30000	10001	10000	10
10024	10082	20011	10011	10000	10010	10000	43097	170749	20010	20	10000	20	30000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  stp w0, w1, [x6], #8
  stp w0, w1, [x7], #8
  stp w0, w1, [x8], #8
  stp w0, w1, [x9], #8
  stp w0, w1, [x10], #8
  stp w0, w1, [x11], #8
  stp w0, w1, [x12], #8
  stp w0, w1, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	80901	160401	80311	80090	80311	80002	240312	1360108	160106	200	80008	200	240024	80005	80000	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	240024	80005	80000	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	240024	80005	80000	100
80205	80108	160154	80137	80017	80140	80002	240312	1360157	160106	200	80008	200	240024	80005	80000	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	240024	80005	80000	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	240024	80005	80000	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	240024	80005	80000	100
80205	80108	160154	80137	80017	80140	80002	240312	1360157	160106	200	80008	200	240024	80005	80000	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	240024	80005	80000	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	240024	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	81146	160305	80215	80090	80214	80002	240042	1360121	160016	20	80008	20	240000	80001	80000	10
80024	80078	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360223	160010	20	80000	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240000	80001	80000	10
80025	80112	160065	80048	80017	80052	80000	240030	1360187	160010	20	80000	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360115	160010	20	80000	20	240000	80001	80000	10

STP (post-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations