Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CBZ (not taken)

Test 1: uops

Code:

  cbz x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	4951	3326	3326	4317	11379	3793	4371	1076	1
1004	667	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1

Test 2: throughput

Count: 8

Code:

  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4
  cbz x0, .+4

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5836

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	55537	84310	84310	85986	241449	80483	80676	80408	1	100
80204	46722	80131	80131	80146	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240903	80301	80449	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80243	1	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5837

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	122240	118519	118519	134702	0	249552	0	0	83184	84084	0	0	81840	1	10
80025	48507	81075	81075	81557	0	399321	0	0	133107	140494	0	0	81664	1	10
80024	47314	80173	80173	80228	0	240309	0	0	80103	80139	0	0	80020	1	10
80024	46695	80011	80011	80010	0	240030	0	0	80010	80020	0	0	80020	1	10
80024	46695	80011	80011	80010	0	240030	0	0	80010	80020	0	0	80020	1	10
80024	46695	80011	80011	80010	0	240030	0	0	80010	80020	0	0	80020	1	10
80025	48029	80830	80830	81208	0	240030	0	0	80010	80020	0	0	80020	1	10
80024	46695	80011	80011	80010	0	240030	0	0	80010	80020	0	0	80020	1	10
80024	46695	80011	80011	80010	0	240030	0	0	80010	80020	0	0	80020	1	10
80024	46695	80011	80011	80010	0	240030	0	0	80010	80020	0	0	80020	1	10