Icestorm: NEGS (register, lsr, 32-bit) measurements

Code:

  negs w0, w0, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000

Test 2: Latency 1->2

Code:

  negs w0, w0, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	529001	10104	10206	10206	20001	10100
10204	20030	20101	20101	10104	529423	10138	10248	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10072	20025	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  negs w0, w1, lsr #17
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	30030	30101	30101	20106	789289	20106	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20205	30060	30117	30117	20144	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20256	30015	20100
20204	30030	30101	30101	20106	789289	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	30030	30011	30011	20015	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789790	20051	20076	20020	30001	20010
20024	30064	30011	30011	20015	789438	20010	20020	20061	30022	20010
20024	30030	30011	30011	20010	789438	20010	20020	20104	30043	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	20010	789789	20053	20073	20020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	20020	30001	20010

Test 4: throughput

Count: 8

Code:

  negs w0, w8, lsr #17
  negs w1, w8, lsr #17
  negs w2, w8, lsr #17
  negs w3, w8, lsr #17
  negs w4, w8, lsr #17
  negs w5, w8, lsr #17
  negs w6, w8, lsr #17
  negs w7, w8, lsr #17

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	53418	160116	160116	0	0	80122	0	1099937	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1104241	80164	80264	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	0	0	80123	0	1116473	80160	80260	80224	160014	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	53380	160042	160042	80048	1104734	80048	80048	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80088	160077	80010
80024	53385	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	80020	160011	80010

NEGS (register, lsr, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations