Icestorm: SBCS (64-bit) measurements

Code:

  sbcs x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000

Test 2: Latency 1->2

Code:

  sbcs x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	251641	10109	10210	30224	10001	10100
10204	10030	10101	10101	10108	251658	10106	10206	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10107	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10109	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	253256	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253613	10068	10068	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010

Test 3: Latency 1->3

Code:

  sbcs x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10109	251563	10106	10206	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	253129	10030	10030	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253284	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010

Test 4: Latency 1->4

Chain cycles: 1

Code:

  sbcs x0, x1, x2
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20201	20201	20208	508746	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	20101	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20021	20021	20029	509756	20030	20032	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010

Test 5: Latency 4->2

Chain cycles: 1

Code:

  sbcs x0, x1, x2
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519312	20107	20212	40232	20001	20100
20204	20030	20101	20101	20107	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519834	20147	20261	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519371	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010

Test 6: Latency 4->3

Chain cycles: 1

Code:

  sbcs x0, x1, x2
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519222	20107	20212	40228	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519507	20017	20032	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	20010

Test 7: Latency 4->4

Code:

  sbcs x0, x1, x2

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10208	253108	10212	10214	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	253220	10030	10032	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253427	10029	10032	30131	10025	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010

Test 8: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  sbcs x0, x8, x9
  ands xzr, xzr, xzr
  sbcs x1, x8, x9
  ands xzr, xzr, xzr
  sbcs x2, x8, x9
  ands xzr, xzr, xzr
  sbcs x3, x8, x9
  ands xzr, xzr, xzr
  sbcs x4, x8, x9
  ands xzr, xzr, xzr
  sbcs x5, x8, x9
  ands xzr, xzr, xzr
  sbcs x6, x8, x9
  ands xzr, xzr, xzr
  sbcs x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7991

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	64082	160115	160115	160122	682068	160115	160216	240284	160047	80100
160204	63935	160109	160109	160113	682133	160115	160216	240230	160015	80100
160204	63921	160112	160112	160116	682095	160122	160222	240224	160012	80100
160204	63936	160115	160115	160119	682499	160118	160220	240230	160011	80100
160204	63892	160112	160112	160118	682061	160115	160216	240224	160011	80100
160204	63936	160111	160111	160115	682065	160115	160216	240230	160015	80100
160204	63918	160111	160111	160115	682142	160115	160216	240224	160011	80100
160204	63920	160110	160110	160115	682240	160116	160216	240230	160015	80100
160204	63899	160110	160110	160115	682149	160115	160216	240230	160011	80100
160205	63955	160149	160149	160156	682133	160115	160216	240230	160015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7985

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	65224	160020	160020	160026	682042	160031	160042	240053	160016	80010
160024	64124	160011	160011	160010	682158	160010	160020	240020	160001	80010
160024	63868	160011	160011	160010	686221	160010	160020	240020	160001	80010
160024	63880	160011	160011	160010	682346	160010	160020	240020	160001	80010
160024	63867	160011	160011	160010	682511	160010	160020	240020	160001	80010
160024	63866	160011	160011	160010	682599	160010	160020	240020	160001	80010
160024	63873	160011	160011	160010	682516	160010	160020	240020	160001	80010
160024	63874	160011	160011	160010	682400	160066	160077	240020	160001	80010
160024	63893	160011	160011	160010	682121	160010	160020	240020	160001	80010
160024	63878	160011	160011	160010	682498	160010	160020	240020	160001	80010

Test 9: throughput

Count: 4

Code:

  fcmp s0, s0
  sbcs x0, x4, x5
  sbcs x1, x4, x5
  sbcs x2, x4, x5
  sbcs x3, x4, x5

Initialization

  mov x4, 5
  mov x5, 6
  mov x6, 7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6208

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24844	50105	40103	10002	40111	10003	309349	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309224	40017	50116	40212	10004	120236	20008	40002	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	310384	40053	50160	40247	10013	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309224	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	120236	20008	40001	40100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6197

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24869	50016	40014	10002	40024	10004	311202	40017	50026	40032	10004	120020	20000	40001	40010
50024	24790	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120047	20006	40002	40010
50024	24798	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311342	40045	50066	40065	10011	120020	20000	40001	40010

Test 10: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  sbcs x0, x7, x8
  sbcs x1, x7, x8
  sbcs x2, x7, x8
  sbcs x3, x7, x8
  sbcs x4, x7, x8
  sbcs x5, x7, x8
  sbcs x6, x7, x8

Initialization

  mov x7, 8
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5844

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	41090	80106	80106	0	80114	541270	80112	80212	210230	80007	70100
80204	40905	80107	80107	0	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	0	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	0	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	0	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	0	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	0	80112	541028	80112	80212	210230	80007	70100
80204	40880	80106	80106	0	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	0	80112	541028	80112	80212	210230	80007	70100
80204	40905	80107	80107	0	80112	541028	80112	80212	210230	80006	70100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5839

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	41021	80033	80033	0	0	80041	0	543427	80036	80036	210020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542624	80020	80020	210020	80011	70010
80024	40899	80027	80027	0	0	80037	0	541666	80020	80020	210020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542624	80020	80020	210020	80011	70010
80025	40915	80060	80060	0	0	80078	0	545066	80020	80020	210020	80011	70010
80024	40899	80021	80021	0	0	80020	0	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	0	0	80020	0	538455	80020	80020	210020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542540	80036	80036	210020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542624	80020	80020	210020	80011	70010

SBCS (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: Latency 4->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 9: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 10: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations