Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
tst x0, x1, lsr #17
mov x0, 1 mov x1, 2
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 2.001
Load/store unit issues: 0.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
Chain cycles: 1
Code:
tst x0, x1, lsr #17 cset x0, cc
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 1 chain cycle): 2.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
20205 | 30060 | 30115 | 30115 | 20142 | 789233 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30215 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30215 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
Result (median cycles for code, minus 1 chain cycle): 2.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
20024 | 30030 | 30011 | 30011 | 20015 | 789401 | 20015 | 20030 | 30020 | 0 | 30001 | 0 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 0 | 30001 | 0 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 0 | 30001 | 0 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 0 | 30001 | 0 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 0 | 30001 | 0 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 0 | 30001 | 0 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 0 | 30001 | 0 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789792 | 20050 | 20076 | 30020 | 0 | 30001 | 0 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 0 | 30001 | 0 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 0 | 30001 | 0 | 0 | 10010 |
Chain cycles: 1
Code:
tst x0, x1, lsr #17 cset x1, cc
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 1 chain cycle): 2.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
20204 | 30030 | 30101 | 30101 | 20106 | 791244 | 20257 | 20379 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30215 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30469 | 30085 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
Result (median cycles for code, minus 1 chain cycle): 2.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
20024 | 30030 | 30011 | 30011 | 20015 | 789401 | 20015 | 20030 | 30020 | 30001 | 10010 |
20025 | 30060 | 30025 | 30025 | 20051 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
Count: 8
Code:
tst x0, x1, lsr #17 tst x0, x1, lsr #17 tst x0, x1, lsr #17 tst x0, x1, lsr #17 tst x0, x1, lsr #17 tst x0, x1, lsr #17 tst x0, x1, lsr #17 tst x0, x1, lsr #17
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.6675
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
80204 | 53405 | 160118 | 160118 | 80124 | 1177651 | 80123 | 80224 | 160252 | 160017 | 100 |
80204 | 53416 | 160118 | 160118 | 80130 | 1177653 | 80125 | 80226 | 160248 | 160014 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177655 | 80123 | 80224 | 160248 | 160014 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177615 | 80123 | 80224 | 160248 | 160014 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177619 | 80123 | 80224 | 160248 | 160014 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177631 | 80123 | 80224 | 160248 | 160014 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177655 | 80123 | 80224 | 160248 | 160014 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177607 | 80123 | 80224 | 160248 | 160014 | 100 |
80205 | 53435 | 160165 | 160165 | 80168 | 1177651 | 80123 | 80224 | 160248 | 160014 | 100 |
80205 | 53435 | 160162 | 160162 | 80163 | 1177607 | 80123 | 80224 | 160248 | 160014 | 100 |
Result (median cycles for code divided by count): 0.6671
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
80024 | 53409 | 160039 | 160039 | 80047 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1172000 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1184194 | 80060 | 80060 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |