Icestorm: TST (register, 32-bit) measurements

Code:

  tst w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	501	1001	1001	1000	3000	1000	1000	2000	1001
1004	396	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	391	1001	1001	1000	3000	1000	1000	2000	1001
1004	389	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	395	1001	1001	1000	3000	1000	1000	2000	1001
1004	391	1001	1001	1000	3000	1000	1000	2000	1001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  tst w0, w1
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519311	20107	20214	30221	20001	10100
20204	20030	20101	20101	20107	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519496	20018	20034	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30116	20015	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  tst w0, w1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519311	20107	20214	30221	20001	10100
20204	20030	20101	20101	20107	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519857	20147	20260	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519516	20018	20034	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519966	20059	20084	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20025	20060	20025	20025	20059	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519956	20058	20080	30116	20016	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 4: throughput

Count: 8

Code:

  tst w0, w1
  tst w0, w1
  tst w0, w1
  tst w0, w1
  tst w0, w1
  tst w0, w1
  tst w0, w1
  tst w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3635

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29106	80113	80113	80118	240468	80156	80256	160240	80012	100
80204	29162	80114	80114	80119	240354	80118	80218	160240	80013	100
80204	29076	80115	80115	80119	240351	80117	80217	160240	80015	100
80204	29081	80112	80112	80117	240354	80118	80220	160240	80013	100
80204	29051	80115	80115	80119	240357	80119	80220	160240	80015	100
80204	29078	80112	80112	80117	240354	80118	80220	160232	80012	100
80204	29026	80115	80115	80119	240360	80120	80220	160240	80015	100
80204	29092	80113	80113	80118	240354	80118	80220	160240	80013	100
80204	29060	80115	80115	80119	240357	80119	80220	160240	80015	100
80204	29066	80113	80113	80118	240351	80117	80220	160240	80013	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3630

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	30097	80037	80037	80041	240168	80041	80044	160020	80011	10
80024	29148	80021	80021	80020	240104	80020	80020	160020	80011	10
80024	29117	80021	80021	80020	240097	80020	80020	160020	80011	10
80024	28932	80021	80021	80020	240106	80020	80020	160020	80011	10
80024	28972	80021	80021	80020	240101	80020	80020	160020	80011	10
80024	29070	80021	80021	80020	240091	80020	80020	160020	80011	10
80024	29127	80021	80021	80020	240114	80020	80020	160020	80011	10
80024	28913	80021	80021	80020	240112	80020	80020	160020	80011	10
80024	28973	80021	80021	80020	240099	80020	80020	160136	80062	10
80024	28989	80021	80021	80020	240105	80020	80020	160020	80011	10

TST (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations