Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PSTL1STRM)

Test 1: uops

Code:

  prfm pstl1strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2442	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2092	1001	1	1000	1000	34926	1000	1000	1000	1	1000
1004	2101	1001	1	1000	1000	34758	1000	1000	1000	1	1000
1004	2086	1001	1	1000	1000	35048	1000	1000	1000	1	1000
1004	2098	1001	1	1000	1000	35060	1000	1000	1000	1	1000
1004	2074	1001	1	1000	1000	34926	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm pstl1strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0105

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	20826	20101	10101	10000	10103	10006	61289	350633	20117	10213	10013	10202	10002	10001	10000	10100
20204	20135	20101	10101	10000	10100	10000	61256	350623	20100	10202	10002	10202	10002	10001	10000	10100
20204	20135	20101	10101	10000	10100	10000	61256	350623	20100	10202	10002	10202	10002	10001	10000	10100
20204	20135	20101	10101	10000	10100	10000	61256	350623	20100	10202	10002	10202	10002	10001	10000	10100
20204	20135	20101	10101	10000	10100	10000	61256	350623	20100	10202	10002	10202	10002	10001	10000	10100
20204	20135	20101	10101	10000	10100	10037	61610	349718	20178	10243	10044	10202	10002	10001	10000	10100
20204	20135	20101	10101	10000	10100	10000	61256	350623	20100	10202	10002	10202	10002	10001	10000	10100
20204	20135	20101	10101	10000	10100	10000	61241	350829	20104	10206	10006	10202	10002	10001	10000	10100
20204	20129	20105	10105	10000	10110	10000	61188	350439	20106	10208	10008	10206	10006	10002	10000	10100
20204	20135	20101	10101	10000	10100	10000	61256	350623	20100	10202	10002	10202	10002	10001	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.9734

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	21148	20013	10013	10000	10017	10000	60979	353561	20010	10020	10000	10020	10000	10001	10000	10010
20024	20295	20011	10011	10000	10010	10000	60993	353585	20010	10020	10000	10020	10000	10001	10000	10010
20024	20295	20011	10011	10000	10010	10000	60993	353585	20010	10020	10000	10020	10000	10001	10000	10010
20024	20295	20011	10011	10000	10010	10000	60993	353585	20010	10020	10000	10020	10000	10001	10000	10010
20024	20295	20011	10011	10000	10010	10000	60993	353585	20010	10020	10000	10020	10000	10001	10000	10010
20024	20295	20011	10011	10000	10010	10000	60993	353585	20010	10020	10000	10020	10000	10001	10000	10010
20024	20295	20011	10011	10000	10010	10000	60993	353585	20010	10020	10000	10020	10000	10001	10000	10010
20024	20295	20011	10011	10000	10010	10000	60993	353585	20010	10020	10000	10020	10000	10001	10000	10010
20024	20295	20011	10011	10000	10010	10000	60993	353585	20010	10020	10000	10020	10000	10001	10000	10010
20024	20295	20011	10011	10000	10010	10000	60993	353585	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm pstl1strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0503

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20938	10101	101	10000	100	10000	300	365120	10100	200	10008	200	10012	1	10000	100
10204	20507	10101	101	10000	100	10000	300	361262	10100	200	10008	200	10014	1	10000	100
10205	20535	10131	101	10030	100	10006	300	355534	10106	200	10012	200	10008	1	10000	100
10204	20473	10101	101	10000	100	10002	300	356704	10102	200	10012	200	10008	1	10000	100
10204	20466	10101	101	10000	100	10000	300	357086	10100	200	10008	200	10008	1	10000	100
10204	20504	10101	101	10000	100	10000	300	356790	10100	200	10004	200	10004	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10004	1	10000	100
10204	20484	10101	101	10000	100	10000	300	356934	10100	200	10004	200	10008	1	10000	100
10204	20503	10101	101	10000	100	10000	300	356986	10100	200	10004	200	10008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0061

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	20056	10011	11	10000	10	10000	30	349210	10010	20	10000	20	10000	1	10000	10
10024	20073	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20071	10011	11	10000	10	10000	30	350006	10010	20	10000	20	10000	1	10000	10
10024	20044	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20083	10011	11	10000	10	10000	30	349718	10010	20	10000	20	10000	1	10000	10
10024	20079	10011	11	10000	10	10000	30	349200	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10