Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDP (32-bit)

Test 1: uops

Code:

  ldp w0, w1, [x6]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
200572510211102010005314100020002000110001000
200455510011100010007290100020002000110001000
200455410011100010005314100020002000110001000
200455410011100010005314100020002000110001000
200455010011100010005314100020002000110001000
200455010011100010005314100020002000110001000
200455010011100010005314100020002000110001000
200455010011100010005314100020002000110001000
200455010011100010005314100020002000110001000
200455010011100010005314100020002000110001000

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp w0, w1, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5020570153401083010710001301301000318558357099754010630212200086022420008300031000040100
5020470049401033010310000301031000318585327110414010630212200086022420008300031000040100
5020470049401033010310000301031000318585327110414010630212200086022420008300031000040100
5020470049401033010310000301031000318585327110414010630212200086022420008300031000040100
5020470049401033010310000301031001618589307111874015130249200356022420008300031000040100
5020470049401033010310000301031000318585327110414010630212200086022420008300031000040100
5020470049401033010310000301031000318585327110414010630212200086022420008300031000040100
5020470049401033010310000301031000318585327110414010630212200086022420008300031000040100
5020570116401113010910002301371000318585597110534010630212200086022420008300031000040100
5020470049401033010310000301031000318585327110414010630212200086022420008300031000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
5002570159400183001710001300401002818642737140544010530107200617313528916735886144031147341
500247004740013300131000030013100001858797711779400103002020000600202000003000310000040010
500247005240013300131000030010100521867380715336401963017520104600202000003000310000040010
500247004740013300131000030010100001859057712019400103002020000600202000003000310000040010
500247004740013300131000030010100001859003711998400103002020000603242010403004010000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010
500247012740013300131000030010100031859562712236400163003220008600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp w0, w1, [x6]
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5020670325401163011310003301641000318577037107344010630212200086022420008300031000040100
5020470042401023010210000301031000318583437109714010630212200086022420008300021000040100
5020470042401023010210000301031000318583437109714010630212200086022420008300021000040100
5020470042401023010210000301031000318583437109714010630212200086022420008300021000040100
5020470042401023010210000301031000318583437109714010630212200086022420008300021000040100
5020470042401023010210000301031000318583437109714010630212200086022420008300021000040100
5020470042401023010210000301031000318583437109714010630212200086022420008300021000040100
5020670120401103010810002301351000318584787110284010630212200086029820034300091000040100
5020470042401023010210000301031000318583437109714010630212200086022420008300021000040100
5020470042401023010210000301031000318583437109714010630212200086022420008300021000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5002570151400183001710001300401000318596357121384001630032200086002020000300021000040010
5002470042400123001210000300101000018588147119254001030020200006002020000300021000040010
5002470042400123001210000300101000018588147119254001030020200006002020000300021000040010
5002470042400123001210000300101000018588147119254001030020200006002020000300021000040010
5002470042400123001210000300101001218587827119534005430059200266002020000300021000040010
5002470042400123001210000300101000018588147119254001030020200006002020000300021000040010
5002470042400123001210000300101001518615337130194006030070200346002020000300021000040010
5002470176400133001310000300101000018593007121234001030020200006004420008300031000040010
5002470040400123001210000300101000018587607119054001030020200006002020000300021000040010
5002470040400123001210000300101000018587607119054001030020200006002020000300021000040010

Test 4: throughput

Count: 8

Code:

  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160205402578012910180028100800123002443508011220016002420016002418000080100
160204401038010910180008100800123002719348011220016002420016002418000080100
160204400988010910180008100800123002442248011220016002420016002418000080100
160204400968010910180008100800123002442248011220016002420016002418000080100
160204400968010910180008100800123002442248011220016002420016002418000080100
160204400968010910180008100800123002442248011220016002420016002418000080100
160204400968010910180008100800123002442248011220016002420016002418000080100
160204400968010910180008100800123002442248011220016002420016002418000080100
160204400968010910180008100800123002442248011220016002420016002418000080100
160204400968010910180008100800123002442248011220016002420016002418000080100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1600254050080044118003310800123024110480022201600242016011218000080010
1600244007180011118000010800123024084480022201600242016000018000080010
1600244004880011118000010800003038416480010201600002016000018000080010
1600244004880011118000010800003038416480010201600002016000018000080010
1600244004880011118000010800003038416480010201600002016000018000080010
1600244004880011118000010800003038416480010201600002016000018000080010
1600244004880011118000010800003038416480010201600002016000018000080010
1600244004880011118000010800003038416480010201600002016000018000080010
1600244004880011118000010800003038416480010201600002016000018000080010
1600244004880011118000010800003038416480010201600002016000018000080010