Icestorm: LDRB (unsigned offset) measurements

Code:

  ldrb w0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	652	1025	1	1024	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	560	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	575	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70153	40108	30107	10001	30130	10003	1859539	693993	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60302	10017	30009	10000	30100
40204	70086	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70156	40018	30017	10001	30040	10003	1859482	694668	40016	30032	10004	60020	10000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60114	10017	30008	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859679	694732	40010	30020	10000	60020	10000	30002	10000	30010
40024	70043	40012	30012	10000	30010	10000	1859571	694688	40010	30020	10000	60020	10000	30002	10000	30010
40024	70047	40012	30012	10000	30010	10000	1859652	694721	40010	30020	10000	60020	10000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	10000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	10000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10015	1862392	695830	40060	30071	10017	60020	10000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	10000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	10000	30002	10000	30010

Test 3: throughput

Count: 8

Code:

  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40232	80127	101	80026	100	80008	300	256190	80108	200	80012	200	80072	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640880	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40290	80041	11	80030	10	80000	30	399998	80010	20	80000	20	80000	1	80000	10
80024	40053	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80057	1	80000	10
80024	40059	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10

LDRB (unsigned offset)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations