Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDRB (unsigned offset)

Test 1: uops

Code:

  ldrb w0, [x6, #8]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056521025110241000811210001000100011000
10045471001110001000811210001000100011000
10045601001110001000811210001000100011000
10045751001110001000804010001000100011000
10045431001110001000804010001000100011000
10045431001110001000804010001000100011000
10045431001110001000804010001000100011000
10045431001110001000816610001000100011000
10045431001110001000804010001000100011000
10045431001110001000804010001000100011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570153401083010710001301301000318595396939934010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046030210017300091000030100
4020470086401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570156400183001710001300401000318594826946684001630032100046002010000300021000030010
4002470040400123001210000300101000018594636946444001030020100006011410017300081000030010
4002470042400123001210000300101000018596796947324001030020100006002010000300021000030010
4002470043400123001210000300101000018595716946884001030020100006002010000300021000030010
4002470047400123001210000300101000018596526947214001030020100006002010000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002010000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002010000300021000030010
4002470040400123001210000300101001518623926958304006030071100176002010000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002010000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002010000300021000030010

Test 3: throughput

Count: 8

Code:

  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540232801271018002610080008300256190801082008001220080072180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640880801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540290800411180030108000030399998800102080000208000018000010
8002440053800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208005718000010
8002440059800111180000108000030640112800102080000208000018000010