Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CINV (32-bit)

Test 1: uops

Code:

  cinv w0, w0, hi
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000

Test 2: Latency 1->2

Code:

  cinv w0, w0, hi
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101082594341010710214302421000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282594741002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010

Test 3: Latency 1->3

Chain cycles: 1

Code:

  cinv w0, w1, hi
  tst x0, 1
  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204200302020120201202085192042021120216402322010110100
20204200302020120201202085194482020820216402322010110100
20204200302020120201202085194482020820216402322010110100
20204200302020120201202085194482020820216402322010110100
20204200302020120201202085194482020820216403262011610100
20204200302020120201202085194482020820216402322010110100
20204200302020120201202085194482020820216402322010110100
20204200302020120201202085194482020820216402322010110100
20204200302020120201202085194482020820216402322010110100
20204200302020120201202085194482020820216402322010110100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024200302002120021200285195092002820034400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010

Test 4: throughput

Count: 8

Code:

  cinv w0, w8, hi
  cinv w1, w8, hi
  cinv w2, w8, hi
  cinv w3, w8, hi
  cinv w4, w8, hi
  cinv w5, w8, hi
  cinv w6, w8, hi
  cinv w7, w8, hi
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802042687380115801158012029163480120802242402668001580100
802042674280115801158012029323680120802242402728001580100
802042674080114801148011929323680120802242402728001580100
802042673780115801158012029323680120802242402728001580100
802042673780115801158012029323680120802242402728001580100
802042673780115801158012029323680120802242402728001580100
802042673780115801158012029323680120802242402728001580100
802042673780115801158012029323680120802242402728001580100
802042673780115801158012029323680120802242402728001580100
802042673780115801158012028576080174802802402728001580100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800242799580038800388005129621680048800522400208001180010
800242680080021800218002035969080105801102400208001180010
800242672280021800218002038943780020800202400208001180010
800242688180130801308012938943780020800202400208001180010
800242703680236802368023538943780020800202400208001180010
800242671880021800218002038943780020800202400208001180010
800252676880080800808010338943780020800202400208001180010
800242671880021800218002038943780020800202400208001180010
800242671880021800218002038943780020800202400208001180010
800242671880021800218002038943780020800202400208001180010