Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDNP (32-bit)

Test 1: uops

Code:

  ldnp w0, w1, [x6]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
200571310311103010006242100020002000110001000
200455410011100010007164100020002000110001000
200455410011100010007164100020002000110001000
200455410011100010007164100020002000110001000
200455510011100010007164100020002000110001000
200455410011100010007164100020002000110001000
200455410011100010007164100020002000110001000
200455410011100010007164100020002000110001000
200455410011100010007164100020002000110001000
200455710011100010004490100020002000110001000

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldnp w0, w1, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502057014840108301070100013013001000318557817099554010630212200086022420008300031000040100
502047004740103301030100003010301000318574137106844010630212200086022420008300021000040100
502047004040102301020100003010301000318582897109514010630212200086022420008300021000040100
502047004040102301020100003010301000318582897109514010630212200086022420008300021000040100
502047004040102301020100003010301001618586797110674015330253200356022420008300021000040100
502047004440102301020100003010301001518586957110984015230250200346022420008300021000040100
502047004040102301020100003010301000318582897109514010630212200086022420008300021000040100
502047004040102301020100003010301000318582897109514010630212200086022420008300021000040100
502047004240102301020100003010301001518588757111614014930250200346022420008300021000040100
502047007640104301040100003010301000318579217108244010630212200086022420008300021000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
500257016440018300171000130040100001857783711409400103002020000600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010
500247004740013300131000030010100001861892713065400103002020000600202000003000310000040010
500247005240013300131000030010100001859408712161400103002020000601202003403000910000040010
500247013940025300221000330043100001858949711975400103002020000600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010
500257007740021300191000230045100001858949711975400103002020000600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldnp w0, w1, [x6]
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0044

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5020570156401083010710001301301000318557817099554010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318585327110454010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470049401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5002570345400183001710001300401000318595817121184001630032200086002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470040400123001210000300101000018589497119754001030020200006002020000300031000040010
5002470040400123001210000300101000018594357121864001030020200006002020000300031000040010
5002470054400123001210000300101000018590577120214001030020200006002020000300031000040010
5002470040400123001210000300101000018589497119754001030020200006012020034300091000040010
5002470043400123001210000300101000018589497119754001030020200006002020000300031000040010
5002470040400123001210000300101000018589497119754001030020200006002020000300031000040010
5002470040400123001210000300101000018589497119754001030020200006002020000300031000040010
5002470040400123001210000300101000018589497119754001030020200006002020000300031000040010

Test 4: throughput

Count: 8

Code:

  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  ldnp w0, w1, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5013

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160205402348013510180034100800123002871968011220016002420016002418000080100
160204401118010810180007100800123002879328011220016002420016002418000080100
160204401058010910180008100800123002547268011220016002420016002418000080100
160204401058010910180008100800123002547268011220016002420016002418000080100
160204401058010910180008100800123002547268011220016002420016002418000080100
160204401058010910180008100800123002547268011220016002420016002418000080100
160204401058010910180008100800123002547268011220016002420016002418000080100
160204401058010910180008100800123002547268011220016002420016002418000080100
160204401058010910180008100800123002547268011220016002420016002418000080100
160204401058010910180008100800123002547268011220016002420016002418000080100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1600254057580040118002910800123024110480022201600242016000018000080010
1600244007280011118000010800003024334080010201600002016000018000080010
1600244014980011118000010800003030550480010201600002016000018000080010
1600244006780011118000010800003024334080010201600002016000018000080010
1600244005080011118000010800003024334080010201600002016000018000080010
1600244005080011118000010800563025431280066201601122016000018000080010
1600244005080011118000010800563024360180066201601122016000018000080010
1600244005080011118000010800003024334080010201600002016000018000080010
1600244005080011118000010800003024334080010201600002016000018000080010
1600244005080011118000010800003024334080010201600002016000018000080010