Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PLDL1STRM)

Test 1: uops

Code:

  prfm pldl1strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2445	1001	1	1000	1000	34910	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34980	1000	1000	1000	1	1000
1004	2078	1001	1	1000	1000	34950	1000	1000	1000	1	1000
1004	2100	1001	1	1000	1000	34990	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34950	1000	1000	1000	1	1000
1004	2101	1001	1	1000	1000	34896	1000	1000	1000	1	1000
1004	2111	1001	1	1000	1000	34830	1000	1000	1000	1	1000
1004	2103	1001	1	1000	1000	34882	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34906	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm pldl1strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0110

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	21164	20103	10103	10000	10102	10006	61405	350465	20118	10214	10014	10203	10003	10001	10000	10100
20204	20101	20106	10106	10000	10105	10000	61720	347761	20106	10208	10008	10204	10004	10001	10000	10100
20204	20064	20103	10103	10000	10104	10000	61371	349593	20104	10206	10006	10204	10004	10003	10000	10100
20204	19998	20101	10101	10000	10100	10006	61467	350141	20118	10214	10014	10204	10004	10003	10000	10100
20204	20214	20105	10105	10000	10110	10006	61405	350465	20118	10214	10014	10214	10014	10006	10000	10100
20204	20110	20106	10106	10000	10112	10006	61405	350465	20118	10214	10014	10214	10014	10006	10000	10100
20204	20110	20106	10106	10000	10112	10006	61405	350465	20118	10214	10014	10214	10014	10006	10000	10100
20204	20110	20106	10106	10000	10112	10039	61902	350107	20182	10245	10046	10214	10014	10006	10000	10100
20204	20110	20106	10106	10000	10112	10006	61405	350465	20118	10214	10014	10214	10014	10006	10000	10100
20204	20110	20106	10106	10000	10112	10006	61405	350465	20118	10214	10014	10214	10014	10006	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.9959

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	20236	20016	10016	10000	10022	10006	60292	347815	20028	10034	10014	10020	10000	10001	10000	10010
20024	19890	20011	10011	10000	10010	10000	61276	347553	20010	10020	10000	10020	10000	10001	10000	10010
20024	19866	20011	10011	10000	10010	10000	60741	346701	20010	10020	10000	10020	10000	10001	10000	10010
20024	19855	20011	10011	10000	10010	10000	61266	349233	20010	10020	10000	10020	10000	10001	10000	10010
20024	20009	20011	10011	10000	10010	10000	61083	347067	20010	10020	10000	10020	10000	10001	10000	10010
20024	19944	20011	10011	10000	10010	10000	60256	347237	20010	10020	10000	10020	10000	10001	10000	10010
20024	19944	20011	10011	10000	10010	10000	60256	347237	20010	10020	10000	10020	10000	10001	10000	10010
20024	19944	20011	10011	10000	10010	10000	60256	347237	20010	10020	10000	10020	10000	10001	10000	10010
20024	20016	20011	10011	10000	10010	10000	60889	347015	20010	10020	10000	10020	10000	10001	10000	10010
20024	20000	20011	10011	10000	10010	10000	59974	347735	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm pldl1strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0958

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20848	10101	101	0	10000	100	0	10057	307	364555	10159	202	10069	200	10004	1	10000	100
10204	20557	10101	101	0	10000	100	0	10006	300	361670	10106	200	10012	200	10008	1	10000	100
10204	20771	10101	101	0	10000	100	0	10004	300	363354	10104	200	10012	200	10008	1	10000	100
10204	20790	10101	101	0	10000	100	0	10004	300	361410	10104	200	10012	200	10004	1	10000	100
10682	23262	10664	444	0	10220	401	0	10004	300	357180	10104	200	10012	200	10012	1	10000	100
10204	20962	10101	101	0	10000	100	0	10048	307	366025	10150	202	10062	200	10012	1	10000	100
73369	171114	68824	37943	70	30811	37197	69	10000	300	348060	10100	200	10008	200	10008	1	10000	100
10204	20011	10101	101	0	10000	100	0	10002	300	345402	10102	200	10012	200	10004	1	10000	100
10204	20058	10101	101	0	10000	100	0	10004	300	345122	10104	200	10012	200	10004	1	10000	100
10204	20512	10101	101	0	10000	100	0	10000	300	357056	10100	200	10006	200	10008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0050

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	20052	10011	11	10000	10	10006	30	349222	10016	20	10012	20	10000	1	10000	10
10024	20119	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10