Icestorm: STRH (post-index) measurements

Code:

  strh w0, [x6], #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1301	2059	1041	1018	1040	1000	4621	17767	2000	1000	2000	1001	1000
1004	1068	2001	1001	1000	1000	1000	4761	17497	2000	1000	2000	1001	1000
1004	1095	2001	1001	1000	1000	1000	4765	17389	2000	1000	2000	1001	1000
1004	1071	2001	1001	1000	1000	1000	4769	17983	2000	1000	2000	1001	1000
1004	1065	2001	1001	1000	1000	1000	4765	17551	2000	1000	2000	1001	1000
1004	1201	2001	1001	1000	1000	1000	4677	17533	2000	1000	2000	1001	1000
1004	1069	2001	1001	1000	1000	1000	4677	18937	2000	1000	2000	1001	1000
1004	1103	2001	1001	1000	1000	1000	4677	18325	2000	1000	2000	1001	1000
1004	1126	2001	1001	1000	1000	1000	4681	17965	2000	1000	2000	1001	1000
1004	1096	2001	1001	1000	1000	1000	4681	18091	2000	1000	2000	1001	1000

Test 2: Latency 2->2

Code:

  strh w0, [x6], #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0095

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10209	11218	20400	10310	10090	10310	10003	57878	171088	20109	200	10010	200	20016	10004	10000	100
10204	10094	20105	10105	10000	10106	10003	63367	170908	20109	200	10010	200	20016	10004	10000	100
10204	10092	20104	10104	10000	10104	10002	43625	171997	20106	200	10008	200	20016	10004	10000	100
10204	10111	20104	10104	10000	10104	10002	43646	171511	20106	200	10008	200	20016	10004	10000	100
10204	10119	20104	10104	10000	10104	10002	43631	170953	20106	200	10008	200	20016	10004	10000	100
10204	10096	20104	10104	10000	10104	10002	43631	170953	20106	200	10008	200	20016	10004	10000	100
10204	10118	20104	10104	10000	10104	10004	43537	172438	20111	200	10011	200	20020	10007	10000	100
10205	10199	20152	10135	10017	10140	10000	43622	170983	20104	200	10008	200	20016	10004	10000	100
10204	10109	20104	10104	10000	10104	10002	43633	171151	20106	200	10008	200	20016	10004	10000	100
10204	10091	20104	10104	10000	10104	10002	43583	171389	20106	200	10008	200	20016	10004	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0144

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10029	11216	20303	10213	10090	10213	10002	43818	171966	20016	20	10008	20	20020	10005	10000	10
10024	10150	20014	10014	10000	10014	10000	43075	171703	20010	20	10000	20	20000	10001	10000	10
10024	10142	20011	10011	10000	10010	10000	43075	171757	20010	20	10000	20	20000	10001	10000	10
10024	10147	20011	10011	10000	10010	10000	43071	171829	20010	20	10000	20	20000	10001	10000	10
10024	10147	20011	10011	10000	10010	10000	43071	171883	20010	20	10000	20	20000	10001	10000	10
10024	10186	20011	10011	10000	10010	10000	43071	171829	20010	20	10000	20	20000	10001	10000	10
10024	10156	20011	10011	10000	10010	10000	43071	171919	20010	20	10000	20	20000	10001	10000	10
10024	10155	20011	10011	10000	10010	10000	43075	172135	20010	20	10000	20	20000	10001	10000	10
10024	10156	20011	10011	10000	10010	10000	43073	171883	20010	20	10000	20	20000	10001	10000	10
10024	10152	20011	10011	10000	10010	10000	43071	171793	20010	20	10000	20	20000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  strh w0, [x6], #8
  strh w0, [x7], #8
  strh w0, [x8], #8
  strh w0, [x9], #8
  strh w0, [x10], #8
  strh w0, [x11], #8
  strh w0, [x12], #8
  strh w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	81214	160403	80313	80090	80313	80002	240312	1360113	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80035	240419	1360971	160175	200	80048	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	160016	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	80941	160305	80215	80090	80214	80002	240042	1360265	160016	20	80008	20	160000	80001	80000	10
80024	80433	160243	80171	80072	80170	80000	240030	1360099	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1360099	160010	20	80000	20	160096	80037	80000	10
80024	80045	160011	80011	80000	80010	80035	240149	1360701	160085	20	80048	20	160416	80197	80000	10
80024	80051	160011	80011	80000	80010	80000	240030	1360099	160010	20	80000	20	160000	80001	80000	10
80024	80051	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80051	160011	80011	80000	80010	80144	240510	1364617	160314	20	80160	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1360099	160010	20	80000	20	160000	80001	80000	10
80024	80437	160243	80171	80072	80170	80000	240030	1360117	160010	20	80000	20	160000	80001	80000	10
80024	80051	160011	80011	80000	80010	80035	240149	1360665	160085	20	80048	20	160000	80001	80000	10

STRH (post-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations