Icestorm: UMSUBL measurements

Code:

  umsubl x0, w0, w1, x2

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	3030	1001	1001	1000	25856	1000	1000	3000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	3000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	3000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	3000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	3000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	3000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	3000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	3000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	3000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	3066	1006	1000

Test 2: Latency 1->2

Code:

  umsubl x0, w0, w1, x2

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	30030	10101	10101	10100	260144	10100	10206	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260259	10114	10232	30224	10001	10100
10204	30030	10101	10101	10100	260150	10100	10206	30218	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010

Test 3: Latency 1->3

Code:

  umsubl x0, w1, w0, x2

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	30030	10101	10101	10100	260144	10100	10206	30224	10001	10100
10204	30030	10101	10101	10100	260150	10100	10206	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	30224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	30030	10021	10021	10020	259907	10020	10030	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30116	10016	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	30020	10011	10010

Test 4: Latency 1->4

Code:

  umsubl x0, w1, w2, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10054	10104	10104	10105	30315	10105	10210	30230	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	30236	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	30236	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	30236	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	30230	10004	10100
10204	10044	10104	10104	10105	30315	10105	10210	30236	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	30236	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	30236	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	30236	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	30236	10004	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10057	10025	10025	10026	30060	10020	10020	30020	10011	10010
10024	10032	10021	10021	10020	30060	10020	10020	30020	10011	10010
10024	10032	10021	10021	10020	30060	10020	10020	30020	10011	10010
10024	10032	10021	10021	10020	30060	10020	10020	30020	10011	10010
10024	10032	10021	10021	10020	30060	10020	10020	30020	10011	10010
10024	10032	10021	10021	10020	30336	10112	10122	30020	10011	10010
10024	10032	10021	10021	10020	30060	10020	10020	30020	10011	10010
10024	10032	10021	10021	10020	30060	10020	10020	30020	10011	10010
10024	10032	10021	10021	10020	30060	10020	10020	30020	10011	10010
10024	10032	10021	10021	10020	30060	10020	10020	30020	10011	10010

Test 5: throughput

Count: 8

Code:

  umsubl x0, w8, w9, x9
  umsubl x1, w8, w9, x9
  umsubl x2, w8, w9, x9
  umsubl x3, w8, w9, x9
  umsubl x4, w8, w9, x9
  umsubl x5, w8, w9, x9
  umsubl x6, w8, w9, x9
  umsubl x7, w8, w9, x9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	80044	80104	80104	80105	240315	80105	80210	240236	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	240236	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	240236	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	240236	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	240236	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	240236	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	240236	80004	80100
80205	80066	80120	80120	80124	240315	80105	80212	240236	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	240236	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	240236	80004	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	80046	80025	80025	80026	240078	80026	80032	240020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	240020	80011	80010
80024	80032	80021	80021	80020	240132	80045	80059	240020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	240020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	240020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	240020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	240020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	240020	80011	80010
80024	80032	80021	80021	80020	240060	80020	80020	240020	80011	80010
80024	80032	80021	80021	80020	240114	80039	80045	240020	80011	80010

UMSUBL

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations