Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADD (sxtw, 32-bit)

Test 1: uops

Code:

  add w0, w0, w1, sxtw
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000

Test 2: Latency 1->2

Code:

  add w0, w0, w1, sxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101072593301010710214202281000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710213202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100292594741002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010

Test 3: Latency 1->3

Code:

  add w0, w1, w0, sxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10205100601011510115101472593121010710214202241000110100
10204100301010110101101072595391010710213202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100292595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010

Test 4: throughput

Count: 8

Code:

  add w0, w8, w9, sxtw
  add w1, w8, w9, sxtw
  add w2, w8, w9, sxtw
  add w3, w8, w9, sxtw
  add w4, w8, w9, sxtw
  add w5, w8, w9, sxtw
  add w6, w8, w9, sxtw
  add w7, w8, w9, sxtw
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802042685380115801158012024036080120802221602428001480100
802042674080114801148011924036080120802241602488001580100
802042674880115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241603608005980100
802042673780115801158012024036080120802241602448001580100
802042687080115801158012024036080120802221602448001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800242800080039800398004426406880020800201600208001180010
800242677580021800218002026064980094800981600208001180010
800242671380021800218002028273880020800201600208001180010
800242671380021800218002028273880020800201600208001180010
800242671380021800218002028273880020800201600208001180010
800242671380021800218002028273880020800201600208001180010
800242671380021800218002028273880020800201600208001180010
800242671380021800218002027740480020800201600208001180010
800242672380021800218002028273880020800201600208001180010
800242671380021800218002028273880020800201600208001180010