Icestorm: LDRB (post-index) measurements

Code:

  ldrb w0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1295	2035	1020	1015	1038	1000	20690	17398	2000	1000	1000	1000	1000	1001	1000	1000
2004	1079	2001	1001	1000	1000	1000	20723	17675	2000	1000	1000	1000	1000	1001	1000	1000
2004	1076	2001	1001	1000	1000	1000	21097	17396	2000	1000	1000	1000	1000	1001	1000	1000
2004	1062	2001	1001	1000	1000	1000	20987	17674	2000	1000	1000	1000	1000	1001	1000	1000
2004	1075	2001	1001	1000	1000	1000	21160	17701	2000	1000	1000	1000	1000	1001	1000	1000
2004	1081	2001	1001	1000	1000	1000	21097	17631	2000	1000	1000	1000	1000	1001	1000	1000
2004	1078	2001	1001	1000	1000	1000	21270	17396	2000	1000	1000	1000	1000	1001	1000	1000
2004	1086	2001	1001	1000	1000	1000	21410	17637	2000	1000	1000	1000	1000	1001	1000	1000
2004	1078	2001	1001	1000	1000	1000	21408	17613	2000	1000	1000	1000	1000	1001	1000	1000
2004	1096	2001	1001	1000	1000	1000	21193	17402	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0281

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71240	50160	40155	10005	40247	10002	1851905	535135	50108	40211	10003	70221	10004	40007	10000	40100
50204	70160	50107	40107	10000	40106	10003	1851576	535121	50109	40212	10004	70221	10004	40006	10000	40100
50205	70264	50122	40120	10002	40140	10003	1852521	535410	50109	40212	10004	70221	10004	40007	10000	40100
50204	70158	50107	40107	10000	40106	10003	1851765	535170	50109	40212	10004	70221	10004	40007	10000	40100
50204	70158	50107	40107	10000	40106	10003	1851765	535170	50109	40212	10004	70221	10004	40007	10000	40100
50204	70158	50107	40107	10000	40106	10003	1851765	535170	50109	40212	10004	70221	10004	40007	10000	40100
50204	70158	50107	40107	10000	40106	10012	1854101	535800	50152	40251	10013	70221	10004	40007	10000	40100
50204	70172	50107	40107	10000	40106	10003	1851765	535170	50109	40212	10004	70221	10004	40007	10000	40100
50204	70160	50107	40107	10000	40106	10003	1851765	535170	50109	40212	10004	70221	10004	40007	10000	40100
50204	70158	50107	40107	10000	40106	10003	1851765	535170	50109	40212	10004	70292	10015	40018	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0117

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50029	71271	50070	40065	10005	40156	10003	1850748	535202	50019	40032	10004	70020	10000	40004	10000	0	40010
50024	70117	50014	40014	10000	40010	10000	1850606	535137	50010	40020	10000	70020	10000	40004	10000	0	40010
50024	70113	50014	40014	10000	40010	10000	1850606	535137	50010	40020	10000	70020	10000	40004	10000	0	40010
50025	70196	50027	40025	10002	40048	10000	1851308	535353	50010	40020	10000	70020	10000	40004	10000	0	40010
50024	70113	50014	40014	10000	40010	10000	1850606	535137	50010	40020	10000	70020	10000	40004	10000	0	40010
50024	70113	50014	40014	10000	40010	10000	1850606	535137	50010	40020	10000	70020	10000	40004	10000	0	40010
50024	70113	50014	40014	10000	40010	10000	1850687	535164	50010	40020	10000	70020	10000	40004	10000	0	40010
50024	70132	50014	40014	10000	40010	10000	1852307	535679	50010	40020	10000	71708	11182	40708	10596	3	40940
50024	70158	50014	40014	10000	40010	10000	1852010	535576	50010	40020	10000	70020	10000	40004	10000	0	40010
50024	70117	50014	40014	10000	40010	10000	1850714	535165	50010	40020	10000	70020	10000	40004	10000	0	40010

Test 3: throughput

Count: 8

Code:

  ldrb w0, [x6], #8
  ldrb w0, [x7], #8
  ldrb w0, [x8], #8
  ldrb w0, [x9], #8
  ldrb w0, [x10], #8
  ldrb w0, [x11], #8
  ldrb w0, [x12], #8
  ldrb w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5406

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44208	160419	80311	80108	80312	80011	240818	637424	160123	80212	80012	80212	80012	80009	80000	80100
160204	43248	160109	80109	80000	80112	80008	240791	644157	160116	80208	80008	80212	80012	80009	80000	80100
160204	43246	160109	80109	80000	80112	80010	240848	638999	160122	80212	80012	80212	80012	80009	80000	80100
160204	43248	160109	80109	80000	80112	80012	240805	644341	160124	80212	80012	80212	80012	80009	80000	80100
160204	43246	160109	80109	80000	80112	80012	240796	642886	160124	80212	80012	80212	80012	80009	80000	80100
160205	43324	160182	80151	80031	80154	80010	240780	645939	160122	80212	80012	80212	80012	80009	80000	80100
160204	43247	160109	80109	80000	80112	80011	240823	636376	160123	80212	80012	80254	80054	80051	80000	80100
160204	43246	160109	80109	80000	80112	80012	240844	641852	160124	80212	80012	80212	80012	80009	80000	80100
160204	43250	160109	80109	80000	80112	80012	240808	645151	160124	80212	80012	80212	80012	80009	80000	80100
160204	43247	160109	80109	80000	80112	80012	240809	636939	160124	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5404

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44476	160334	80223	80111	80226	80011	240343	644448	160034	80033	80013	80032	80012	80009	80000	80010
160024	43228	160011	80011	80000	80010	80000	240304	644729	160010	80020	80000	80020	80000	80001	80000	80010
160024	43354	160022	80019	80003	80022	80010	240353	644232	160032	80032	80012	80032	80012	80009	80000	80010
160024	43233	160019	80019	80000	80022	80010	240340	644287	160032	80032	80012	80032	80012	80009	80000	80010
160024	43230	160019	80019	80000	80022	80010	240383	646098	160032	80032	80012	80032	80012	80009	80000	80010
160024	43232	160019	80019	80000	80022	80000	240304	641329	160010	80020	80000	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	645105	160010	80020	80000	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	645847	160010	80020	80000	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	644358	160010	80020	80000	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	641728	160010	80020	80000	80020	80000	80001	80000	80010

LDRB (post-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations