Icestorm: AUTDA measurements

Code:

  autda x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	? int output thing (e9)	? int retires (ef)
1004	6029	1001	1001	1000	52825	1011	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000

Test 2: Latency 1->1

Code:

  autda x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	60029	10201	10201	10200	0	530325	0	0	10200	200	0	0	200	10101	10100
10204	60029	10201	10201	10200	0	530325	0	0	10200	200	0	0	200	10101	10100
10204	60029	10201	10201	10200	0	530325	0	0	10200	200	0	0	200	10101	10100
10204	60029	10201	10201	10200	0	530325	0	0	10200	200	0	0	200	10101	10100
10204	60029	10201	10201	10200	0	530325	0	0	10200	200	0	0	200	10101	10100
10204	60029	10201	10201	10200	0	530325	0	0	10200	200	0	0	200	10101	10100
10204	60029	10201	10201	10200	0	530325	0	0	10200	200	0	0	200	10101	10100
10204	60029	10201	10201	10200	0	530325	0	0	10200	200	0	0	200	10104	10100
10204	60029	10201	10201	10200	0	530325	0	0	10200	200	0	0	200	10101	10100
10204	60029	10201	10201	10200	0	530325	0	0	10200	200	0	0	200	10101	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10025	60058	10024	10024	10031	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529885	10031	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  autda x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	70029	20201	20201	20202	1429562	20202	10204	20208	20101	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	20101	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	20101	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	20101	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	20101	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20336	20125	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20242	20106	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	20101	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	20101	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	20101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	70029	20021	20021	20022	1429191	20022	10024	20028	0	0	20011	0	0	30010
30024	70029	20021	20021	20020	1429198	20020	10020	20020	0	0	20011	0	0	30010
30024	70029	20021	20021	20020	1429198	20020	10020	20020	0	0	20011	0	0	30010
30024	70029	20021	20021	20020	1429198	20020	10020	20020	0	0	20011	0	0	30010
30024	70029	20021	20021	20020	1429198	20020	10020	20020	0	0	20011	0	0	30010
30024	70029	20021	20021	20020	1429198	20020	10020	20020	0	0	20011	0	0	30010
30024	70029	20021	20021	20020	1429198	20020	10020	20020	0	0	20011	0	0	30010
30024	70029	20021	20021	20022	1429198	20020	10020	20020	0	0	20011	0	0	30010
30024	70029	20021	20021	20020	1429198	20020	10020	20020	0	0	20011	0	0	30010
30024	70029	20021	20021	20020	1429198	20020	10020	20020	0	0	20011	0	0	30010

Test 4: throughput

Count: 8

Code:

  autda x0, x8
  autda x1, x8
  autda x2, x8
  autda x3, x8
  autda x4, x8
  autda x5, x8
  autda x6, x8
  autda x7, x8

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	160030	80201	80201	0	80202	1360379	80202	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	0	80202	1360481	80202	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	0	80202	1360481	80202	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	0	80202	1360580	80220	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	0	80202	1360481	80202	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	0	80202	1360481	80202	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	0	80202	1360481	80202	200	200	0	0	80101	0	0	80100
80205	160064	80211	80211	0	80220	1360481	80202	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	0	80202	1360566	80219	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	0	80202	1360481	80202	200	200	0	0	80101	0	0	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	160030	80021	80021	80022	0	1359890	0	80022	20	0	20	80011	80010
80024	160030	80021	80021	80022	0	1359880	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010

AUTDA

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations