Icestorm: CMN (shifted immediate, 32-bit) measurements

Code:

  cmn w0, #3, lsl #12

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	556	1001	1001	1000	3000	1000	1000	1000	1001
1004	396	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	389	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	393	1001	1001	1000	3000	1000	1000	1000	1001
1004	390	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  cmn w0, #3, lsl #12
  cset x0, cc

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519442	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519638	20018	20036	20032	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20025	20060	20025	20025	20050	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010

Test 3: throughput

Count: 8

Code:

  cmn w0, #3, lsl #12
  cmn w0, #3, lsl #12
  cmn w0, #3, lsl #12
  cmn w0, #3, lsl #12
  cmn w0, #3, lsl #12
  cmn w0, #3, lsl #12
  cmn w0, #3, lsl #12
  cmn w0, #3, lsl #12

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3634

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29226	80113	80113	80118	240354	80118	80220	80220	80015	100
80204	29070	80114	80114	80118	240354	80118	80220	80220	80015	100
80204	29071	80113	80113	80118	240357	80119	80220	80220	80013	100
80204	29051	80115	80115	80119	240354	80118	80218	80220	80015	100
80204	29072	80112	80112	80117	240357	80119	80220	80220	80013	100
80204	29082	80115	80115	80119	240351	80117	80220	80220	80013	100
80204	29118	80115	80115	80119	240354	80118	80220	80220	80013	100
80204	29075	80112	80112	80117	240354	80118	80220	80220	80015	100
80204	29058	80115	80115	80120	240357	80119	80220	80220	80013	100
80204	29051	80115	80115	80119	240360	80120	80220	80220	80013	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3628

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	29977	80035	80035	80039	240090	80020	80020	80020	80011	10
80024	29099	80021	80021	80020	240070	80020	80020	80020	80011	10
80024	28979	80021	80021	80020	240077	80020	80020	80020	80011	10
80024	28955	80021	80021	80020	240084	80020	80020	80020	80011	10
80024	29084	80021	80021	80020	240080	80020	80020	80020	80011	10
80024	29028	80021	80021	80020	240100	80020	80020	80020	80011	10
80024	28979	80021	80021	80020	240077	80020	80020	80020	80011	10
80024	28876	80021	80021	80020	240079	80020	80020	80020	80011	10
80024	29860	80035	80035	80039	240184	80058	80058	80044	80027	10
80025	29101	80075	80075	80079	240066	80020	80020	80020	80011	10

CMN (shifted immediate, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations