Icestorm: LDNP (64-bit) measurements

Code:

  ldnp x0, x1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	686	1021	1	1020	1000	6242	1000	2000	2000	1	1000	1000
2004	554	1001	1	1000	1000	7290	1000	2000	2000	1	1000	1000
2004	554	1001	1	1000	1000	7290	1000	2000	2000	1	1000	1000
2004	554	1001	1	1000	1000	7290	1000	2000	2000	1	1000	1000
2004	554	1001	1	1000	1000	7290	1000	2000	2000	1	1000	1000
2004	557	1001	1	1000	1000	7290	1000	2000	2000	1	1000	1000
2004	555	1001	1	1000	1000	7290	1000	2000	2000	1	1000	1000
2004	554	1001	1	1000	1000	7290	1000	2000	2000	1	1000	1000
2004	554	1001	1	1000	1000	7290	1000	2000	2000	1	1000	1000
2004	554	1001	1	1000	1000	7290	1000	2000	2000	1	1000	1000

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldnp x0, x1, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	70150	40108	30107	10001	30130	10003	1857602	710754	40106	30212	20008	60300	20034	30009	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60300	20034	30009	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	70156	40018	30017	10001	30040	10003	1857856	711470	40016	30032	20008	60020	20000	30003	10000	40010
50024	70049	40013	30013	10000	30010	10000	1859003	711995	40010	30020	20000	60020	20000	30003	10000	40010
50024	70049	40013	30013	10000	30010	10000	1859003	711995	40010	30020	20000	60020	20000	30003	10000	40010
50024	70049	40013	30013	10000	30010	10000	1859003	711995	40010	30020	20000	60020	20000	30003	10000	40010
50024	70049	40013	30013	10000	30010	10000	1859084	712028	40010	30020	20000	60020	20000	30003	10000	40010
50024	70057	40013	30013	10000	30010	10052	1865604	714557	40194	30174	20104	60120	20034	30009	10000	40010
50024	70049	40013	30013	10000	30010	10000	1859003	711995	40010	30020	20000	60020	20000	30003	10000	40010
50024	70049	40013	30013	10000	30010	10000	1859003	711995	40010	30020	20000	60020	20000	30003	10000	40010
50024	70051	40013	30013	10000	30010	10000	1859273	712105	40010	30020	20000	60322	20104	30039	10000	40010
50025	70079	40021	30019	10002	30045	10000	1859516	712208	40010	30020	20000	60020	20000	30003	10000	40010

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldnp x0, x1, [x6]
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50206	70175	40116	30113	10003	30162	10003	1856490	710138	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858532	711043	40106	30212	20008	60224	20008	30003	10000	40100
50204	70049	40103	30103	10000	30103	10003	1858613	711079	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100
50204	70047	40103	30103	10000	30103	10003	1858478	711021	40106	30212	20008	60224	20008	30003	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	70163	40018	30017	10001	30040	10016	1862486	713410	40061	30069	20035	60020	20000	30003	10000	40010
50024	70047	40013	30013	10000	30010	10000	1858976	711987	40010	30020	20000	60020	20000	30003	10000	40010
50024	70047	40013	30013	10000	30010	10000	1859084	712033	40010	30020	20000	60020	20000	30003	10000	40010
50024	70047	40013	30013	10000	30010	10000	1859057	712023	40010	30020	20000	60020	20000	30003	10000	40010
50024	70047	40013	30013	10000	30010	10000	1859192	712073	40010	30020	20000	60020	20000	30003	10000	40010
50024	70102	40013	30013	10000	30010	10000	1860731	712635	40010	30020	20000	60120	20034	30009	10000	40010
50024	70047	40013	30013	10000	30010	10000	1858949	711975	40010	30020	20000	60020	20000	30003	10000	40010
50024	70047	40013	30013	10000	30010	10000	1858949	711975	40010	30020	20000	60020	20000	30003	10000	40010
50024	70109	40013	30013	10000	30010	10000	1859165	712065	40010	30020	20000	60020	20000	30003	10000	40010
50024	70050	40013	30013	10000	30010	10000	1858949	711975	40010	30020	20000	60020	20000	30003	10000	40010

Test 4: throughput

Count: 8

Code:

  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5012

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	40268	80131	101	80030	100	80012	300	244070	0	80112	200	160024	0	200	160024	1	80000	80100
160204	40107	80109	101	80008	100	80012	300	254600	0	80112	200	160024	0	200	160024	1	80000	80100
160204	40098	80109	101	80008	100	80012	300	254600	0	80112	200	160024	0	200	160024	1	80000	80100
160204	40098	80109	101	80008	100	80012	300	254600	0	80112	200	160024	0	200	160024	1	80000	80100
160204	40098	80109	101	80008	100	80012	300	254600	0	80112	200	160024	0	200	160024	1	80000	80100
160204	40098	80109	101	80008	100	80012	300	254600	0	80112	200	160024	0	200	160024	1	80000	80100
160204	40098	80109	101	80008	100	80012	300	254600	0	80112	200	160024	0	200	160024	1	80000	80100
160204	40098	80109	101	80008	100	80012	300	254600	0	80112	200	160024	0	200	160024	1	80000	80100
160204	40098	80109	101	80008	100	80012	300	254600	0	80112	200	160024	0	200	160024	1	80000	80100
160204	40098	80109	101	80008	100	80012	300	254600	0	80112	200	160024	0	200	160024	1	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	40619	80039	11	80028	10	80012	30	241230	80022	20	160024	20	160000	1	80000	80010
160024	40070	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	431406	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010
160024	40057	80011	11	80000	10	80000	30	243466	80010	20	160000	20	160000	1	80000	80010

LDNP (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations