Icestorm: LDRSW (pre-index) measurements

Code:

  ldrsw x0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1245	2031	1018	1013	1036	1000	20712	17389	2000	1000	1000	1000	1000	1001	1000	1000
2004	1076	2001	1001	1000	1000	1000	20582	17840	2000	1000	1000	1000	1000	1001	1000	1000
2004	1073	2001	1001	1000	1000	1000	21139	17716	2000	1000	1000	1000	1000	1001	1000	1000
2004	1083	2001	1001	1000	1000	1000	20877	17934	2000	1000	1000	1000	1000	1001	1000	1000
2004	1086	2001	1001	1000	1000	1000	20999	17515	2000	1000	1000	1000	1000	1001	1000	1000
2004	1086	2001	1001	1000	1000	1000	21065	17634	2000	1000	1000	1000	1000	1001	1000	1000
2004	1081	2001	1001	1000	1000	1000	20889	17982	2000	1000	1000	1000	1000	1001	1000	1000
2004	1082	2001	1001	1000	1000	1000	21108	17589	2000	1000	1000	1000	1000	1001	1000	1000
2004	1076	2001	1001	1000	1000	1000	21056	17623	2000	1000	1000	1000	1000	1001	1000	1000
2004	1084	2001	1001	1000	1000	1000	21226	17588	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0276

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71263	50161	40156	10005	40247	10003	1851775	535160	50109	40212	10004	70221	10004	40006	10000	40100
50204	70153	50106	40106	10000	40106	10003	1851576	535169	50109	40212	10004	70221	10004	40006	10000	40100
50204	70201	50106	40106	10000	40106	10003	1852629	535517	50109	40212	10004	70221	10004	40006	10000	40100
50204	70160	50106	40106	10000	40106	10003	1852683	535538	50109	40212	10004	70221	10004	40006	10000	40100
50204	70178	50106	40106	10000	40106	10003	1851576	535169	50109	40212	10004	70221	10004	40006	10000	40100
50204	70151	50106	40106	10000	40106	10012	1853373	535629	50152	40251	10013	70221	10004	40006	10000	40100
50204	70151	50106	40106	10000	40106	10003	1851576	535169	50109	40212	10004	70221	10004	40006	10000	40100
50204	70151	50106	40106	10000	40106	10013	1856148	536628	50153	40253	10015	70988	10118	40142	10000	40100
50204	70134	50106	40106	10000	40106	10003	1851846	535259	50109	40212	10004	70221	10004	40006	10000	40100
50204	70151	50106	40106	10000	40106	10003	1851576	535169	50109	40212	10004	70221	10004	40006	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0094

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50030	71484	50083	40076	10007	40190	10003	1852935	535961	50019	40032	10004	70041	10004	40004	10000	40010
50024	70119	50014	40014	10000	40010	10000	1850039	534998	50010	40020	10000	70020	10000	40003	10000	40010
50024	70092	50013	40013	10000	40010	10000	1850039	534998	50010	40020	10000	70020	10000	40003	10000	40010
50024	70092	50013	40013	10000	40010	10000	1850039	534998	50010	40020	10000	70109	10013	40014	10000	40010
50024	70132	50013	40013	10000	40010	10000	1851497	535483	50010	40020	10000	70020	10000	40003	10000	40010
50024	70186	50013	40013	10000	40010	10000	1850039	534998	50010	40020	10000	70020	10000	40003	10000	40010
50024	70092	50013	40013	10000	40010	10000	1850039	534998	50010	40020	10000	70020	10000	40003	10000	40010
50024	70092	50013	40013	10000	40010	10000	1850039	534998	50010	40020	10000	70112	10015	40014	10000	40010
50024	70092	50013	40013	10000	40010	10000	1850039	534998	50010	40020	10000	70020	10000	40003	10000	40010
50024	70096	50013	40013	10000	40010	10000	1850633	535196	50010	40020	10000	70020	10000	40003	10000	40010

Test 3: throughput

Count: 8

Code:

  ldrsw x0, [x6, #8]!
  ldrsw x0, [x7, #8]!
  ldrsw x0, [x8, #8]!
  ldrsw x0, [x9, #8]!
  ldrsw x0, [x10, #8]!
  ldrsw x0, [x11, #8]!
  ldrsw x0, [x12, #8]!
  ldrsw x0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5403

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160204	43256	160109	80109	80000	80112	80011	240485	642420	160123	80212	80012	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80009	240485	642595	160121	80212	80012	80212	80012	80009	80000	80100
160205	43536	160182	80151	80031	80154	80012	240578	642135	160124	80212	80012	80212	80012	80009	80000	80100
160204	43214	160109	80109	80000	80112	80012	240485	642917	160124	80212	80012	80212	80012	80009	80000	80100
160204	43217	160109	80109	80000	80112	80011	240485	642333	160123	80212	80012	80212	80012	80009	80000	80100
160204	43216	160107	80107	80000	80108	80010	240485	641045	160122	80212	80012	80212	80012	80009	80000	80100
160204	43217	160110	80109	80001	80112	80009	240485	641198	160121	80212	80012	80212	80012	80009	80000	80100
160205	43476	160186	80151	80035	80154	80012	240601	644247	160124	80212	80012	80212	80012	80009	80000	80100
160204	43218	160109	80109	80000	80112	80008	240473	642955	160116	80208	80008	80212	80012	80009	80000	80100
160204	43216	160109	80109	80000	80112	80008	240473	642406	160116	80208	80008	80292	80092	80089	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5402

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160029	44382	160326	80220	80106	80223	80008	240215	644223	160030	80032	80012	80020	80000	0	80001	80000	0	80010
160024	43216	160011	80011	80000	80010	80000	240179	645048	160010	80020	80000	80020	80000	0	80001	80000	0	80010
160024	43215	160011	80011	80000	80010	80000	240179	644737	160010	80020	80000	80020	80000	0	80001	80000	0	80010
160025	43284	160092	80061	80031	80064	80000	240272	645927	160010	80020	80000	80020	80000	0	80001	80000	0	80010
160024	43215	160011	80011	80000	80010	80000	240179	644585	160010	80020	80000	80020	80000	0	80001	80000	0	80010
160024	43217	160011	80011	80000	80010	80000	240179	640614	160010	80020	80000	80020	80000	0	80001	80000	0	80010
160024	43215	160011	80011	80000	80010	80000	240179	639211	160010	80020	80000	80020	80000	0	80001	80000	0	80010
160024	43215	160011	80011	80000	80010	80000	240179	642359	160010	80020	80000	80020	80000	0	80001	80000	0	80010
160024	43215	160011	80011	80000	80010	80000	240179	639894	160010	80020	80000	80020	80000	0	80001	80000	0	80010
160025	43304	160094	80061	80033	80064	80000	240272	641777	160010	80020	80000	80020	80000	0	80001	80000	0	80010

LDRSW (pre-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations