Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

TBZ (taken)

Test 1: uops

Code:

  tbz x0, #1, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	9942	5892	5892	8100	6504	2168	2227	1009	1
1004	3391	1001	1001	1000	3000	1000	1000	1000	1
1004	2614	1001	1001	1000	3000	1000	1000	1000	1
1004	2551	1001	1001	1000	3000	1000	1000	1000	1
1004	2752	1001	1001	1000	3000	1000	1000	8981	1
1004	4081	1254	1254	1323	3009	1003	1003	1000	1
1004	2815	1001	1001	1000	3000	1000	1000	1000	1
1004	2629	1001	1001	1000	3000	1000	1000	1000	1
1004	2683	1001	1001	1000	3000	1000	1000	1000	1
1004	2737	1001	1001	1000	3000	1000	1000	9378	1

Test 2: throughput

Count: 8

Code:

  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4

Initialization

  mov x0, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0614

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	95223	83484	83484	84910	240318	80106	80206	80209	1	100
80204	85259	80105	80105	80106	240318	80106	80206	80223	1	100
80204	85006	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84896	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84908	80105	80105	80106	240318	80106	80206	80240	1	100
80204	84370	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84930	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84916	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84928	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84934	80105	80105	80106	240318	80106	80206	80206	1	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.9552

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	369959	118049	118049	132112	240336	80112	80122	80030	1	10
80024	317327	80022	80022	80022	240068	80023	80033	80021	1	10
80024	316878	80012	80012	80011	240033	80011	80021	80021	1	10
80025	316593	80025	80025	80032	240033	80011	80021	80021	1	10
80024	316875	80012	80012	80011	240033	80011	80021	80021	1	10
80025	316893	80015	80015	80015	240033	80011	80021	80021	1	10
80024	316195	80012	80012	80011	240033	80011	80021	80021	1	10
80025	316231	80020	80020	80020	240033	80011	80021	80021	1	10
80024	316788	80012	80012	80011	240033	80011	80021	80021	1	10
80025	316826	80015	80015	80015	240033	80011	80021	80039	1	10