Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stxrh w0, w1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 1.000
Issues: 1.000
Integer unit issues: 0.001
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 71483 | 40191 | 1437 | 288 | 1149 | 245 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33894 | 1001 | 1 | 1000 | 0 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34284 | 1001 | 1 | 1000 | 0 | 1000 | 4003 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34338 | 1001 | 1 | 1000 | 0 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34065 | 1001 | 1 | 1000 | 0 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34174 | 1001 | 1 | 1000 | 0 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34088 | 1001 | 1 | 1000 | 0 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34092 | 1001 | 1 | 1000 | 0 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33957 | 1001 | 1 | 1000 | 0 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33918 | 1001 | 1 | 1000 | 0 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
Code:
stxrh w0, w1, [x6] add x6, x6, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.1099
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20206 | 21457 | 20199 | 10163 | 10036 | 10165 | 10005 | 35517 | 221708 | 20110 | 10205 | 10005 | 10205 | 20010 | 10004 | 10000 | 10100 |
| 20204 | 21070 | 20103 | 10103 | 10000 | 10104 | 10034 | 35809 | 224484 | 20168 | 10234 | 10034 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21211 | 20104 | 10104 | 10000 | 10103 | 10004 | 35473 | 222803 | 20108 | 10204 | 10004 | 10205 | 20010 | 10004 | 10000 | 10100 |
| 20204 | 21109 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 223486 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21090 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 224262 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21061 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 222747 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21103 | 20103 | 10103 | 10000 | 10104 | 10034 | 35794 | 223482 | 20170 | 10236 | 10034 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21069 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 222487 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21070 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 222763 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21080 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 223017 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
Result (median cycles for code): 2.1074
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20026 | 21355 | 20106 | 10070 | 10036 | 10073 | 10004 | 35264 | 223191 | 20018 | 10024 | 10004 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21070 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 222956 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21013 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 222164 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21055 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 221871 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21034 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 222371 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21004 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 221720 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21001 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 222039 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21044 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 222960 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21077 | 20011 | 10011 | 10000 | 10010 | 10034 | 35588 | 224070 | 20078 | 10054 | 10034 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 20998 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 222421 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
Code:
stxrh w0, w1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0047
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 10205 | 20158 | 10119 | 101 | 10018 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 529053 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30055 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
Result (median cycles for code): 3.0047
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 10025 | 20154 | 10029 | 11 | 0 | 10018 | 10 | 0 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 0 | 10000 | 10 | 0 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 0 | 10000 | 10 | 0 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 0 | 10000 | 10 | 0 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 0 | 10000 | 10 | 0 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 0 | 10000 | 10 | 0 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 0 | 10000 | 10 | 0 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 0 | 10000 | 10 | 0 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 0 | 10000 | 10 | 0 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 0 | 10000 | 10 | 0 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |