Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STLXR (32-bit)

Test 1: uops

Code:

  stlxr w0, w1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	3159	1019	1	1018	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000
1004	3047	1001	1	1000	1000	51855	1000	1000	2000	1	1000

Test 2: throughput

Code:

  stlxr w0, w1, [x6]
  add x6, x6, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.1348

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20209	31947	20321	10231	0	10090	10230	0	10003	35473	351181	20106	10203	10003	10203	20006	10004	10000	10100
29863	116360	28971	15273	33	13665	15107	32	10002	35392	350876	20103	10201	10002	10202	20004	10003	10000	10100
20204	31322	20103	10103	0	10000	10102	0	10002	35491	351059	20104	10202	10002	10203	20006	10004	10000	10100
20204	31362	20104	10104	0	10000	10103	0	10002	35491	351217	20104	10202	10002	10202	20004	10003	10000	10100
20204	31339	20103	10103	0	10000	10102	0	10002	35491	351247	20104	10202	10002	10202	20004	10003	10000	10100
20204	31345	20103	10103	0	10000	10102	0	10002	35491	351320	20104	10202	10002	10202	20004	10003	10000	10100
20204	31343	20103	10103	0	10000	10102	0	10002	35491	351259	20104	10202	10002	10202	20004	10003	10000	10100
20204	31341	20103	10103	0	10000	10102	0	10002	35491	351245	20104	10202	10002	10202	20004	10003	10000	10100
20204	31347	20103	10103	0	10000	10102	0	10002	35491	351376	20104	10202	10002	10202	20004	10003	10000	10100
20204	31342	20103	10103	0	10000	10102	0	10002	35491	351311	20104	10202	10002	10202	20004	10003	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.1437

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20029	31980	20228	10138	10090	10137	10002	35244	352809	20014	10022	10002	10020	20000	10001	10000	10010
20024	31454	20011	10011	10000	10010	10000	35235	352438	20010	10020	10000	10020	20000	10001	10000	10010
20024	31444	20011	10011	10000	10010	10000	35235	352470	20010	10020	10000	10020	20000	10001	10000	10010
20024	31440	20011	10011	10000	10010	10000	35235	352521	20010	10020	10000	10020	20000	10001	10000	10010
20024	31426	20011	10011	10000	10010	10000	35235	352641	20010	10020	10000	10020	20000	10001	10000	10010
20024	31441	20011	10011	10000	10010	10000	35235	352346	20010	10020	10000	10020	20000	10001	10000	10010
20024	31442	20011	10011	10000	10010	10000	35235	352310	20010	10020	10000	10020	20000	10001	10000	10010
20024	31443	20011	10011	10000	10010	10000	35235	352450	20010	10020	10000	10020	20000	10001	10000	10010
20024	31430	20011	10011	10000	10010	10000	35235	352343	20010	10020	10000	10020	20000	10001	10000	10010
20024	31413	20011	10011	10000	10010	10000	35235	352095	20010	10020	10000	10020	20000	10001	10000	10010

Test 3: throughput

Code:

  stlxr w0, w1, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10205	30397	10119	101	10018	100	10000	300	528855	10100	200	10004	200	20008	1	10000	100
10204	30047	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30040	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30096	10101	101	10000	100	10000	300	528713	10100	200	10004	200	20008	1	10000	100
10204	30050	10101	101	10000	100	10000	300	528929	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10025	30153	10029	11	0	10018	10	0	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30047	10011	11	0	10000	10	0	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	0	10000	10	0	10072	30	529365	10082	20	10092	20	20096	1	10000	10
10024	30047	10011	11	0	10000	10	0	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	0	10000	10	0	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	0	10000	10	0	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	0	10000	10	0	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	0	10000	10	0	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	0	10000	10	0	10000	30	528713	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	0	10000	10	0	10000	30	528713	10010	20	10000	20	20000	1	10000	10