Icestorm: UDIV (slow, 32-bit) measurements

Code:

  udiv w0, w1, w2

Initialization

  mov w1, #0xffffffff
  mov w2, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Chain cycles: 2

Code:

  udiv w0, w1, w2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov w1, #0xffffffff
  mov w2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	150030	40201	40201	0	30203	4018042	30203	30210	60224	0	40101	0	0	30100
30204	150030	40201	40201	0	30203	4018070	30203	30212	60224	0	40101	0	0	30100
30204	150030	40201	40201	0	30203	4018070	30203	30212	60224	0	40101	0	0	30100
30205	150060	40204	40204	0	30231	4018070	30203	30212	60224	0	40101	0	0	30100
30204	150030	40201	40201	0	30203	4018070	30203	30212	60224	0	40101	0	0	30100
30204	150030	40201	40201	0	30203	4018070	30203	30212	60224	0	40101	0	0	30100
30204	150030	40201	40201	0	30203	4018070	30203	30212	60224	0	40101	0	0	30100
30205	150060	40204	40204	0	30232	4018070	30203	30212	60224	0	40101	0	0	30100
30204	150030	40201	40201	0	30203	4018070	30203	30212	60224	0	40101	0	0	30100
30204	150030	40201	40201	0	30203	4018070	30203	30212	60224	0	40101	0	0	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	150030	40011	40011	30013	4018317	30013	30030	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018679	30042	30068	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018670	30040	30065	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010

Test 3: Latency 1->3

Chain cycles: 2

Code:

  udiv w0, w1, w2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov w1, #0xffffffff
  mov w2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
30204	150030	40201	40201	0	0	30203	0	4018070	30203	30212	60556	222	40216	88	30230
30204	150030	40201	40201	0	0	30203	0	4018070	30203	30212	60224	0	40101	0	30100
30204	150030	40201	40201	0	0	30203	0	4018070	30203	30212	60224	0	40101	0	30100
30204	150030	40201	40201	0	0	30203	0	4018070	30203	30212	60224	0	40101	0	30100
30205	150060	40204	40204	0	0	30230	0	4018070	30203	30212	60224	0	40101	0	30100
30204	150030	40201	40201	0	0	30203	0	4018070	30203	30212	60224	0	40101	0	30100
30204	150030	40201	40201	0	0	30203	0	4018070	30203	30212	60224	0	40101	0	30100
30204	150030	40201	40201	0	0	30203	0	4018070	30203	30212	60224	0	40101	0	30100
30205	150060	40206	40206	0	0	30234	0	4018070	30203	30212	60224	0	40101	0	30100
30204	150030	40201	40201	0	0	30203	0	4018070	30203	30212	60224	0	40101	0	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	150030	40011	40011	30013	4018298	30010	30020	60124	40004	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60116	40004	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60116	40004	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010

Test 4: throughput

Code:

  udiv w0, w1, w2

Initialization

  mov w1, #0xffffffff
  mov w2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	130030	20101	20101	10100	1159832	10100	10206	20216	0	20001	0	0	10100
10204	130030	20101	20101	10100	1159948	10109	10222	20216	0	20001	0	0	10100
10204	130030	20101	20101	10100	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	10100	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	10100	1159948	10109	10224	20216	0	20001	0	0	10100
10204	130030	20101	20101	10100	1159948	10109	10222	20212	0	20001	0	0	10100
10204	130030	20101	20101	10100	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	10100	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	10100	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	10100	1159948	10109	10224	20216	0	20001	0	0	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	130030	20021	20021	10020	1159708	10029	10043	20020	20011	10010
10024	130030	20021	20021	10020	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	10020	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	10020	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	10020	1159592	10020	10020	20020	20011	10010
10025	130060	20024	20024	10029	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	10020	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	10020	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	10020	1159592	10020	10020	20062	20014	10010
10025	130060	20024	20024	10029	1159592	10020	10020	20020	20011	10010

UDIV (slow, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations