Icestorm: NEGS (register, asr, 64-bit) measurements

Code:

  negs x0, x0, asr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000

Test 2: Latency 1->2

Code:

  negs x0, x0, asr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	529001	10104	10206	10208	20001	10100
10204	20030	20101	20101	10104	529044	10104	10206	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	10208	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529272	10025	10032	10030	20011	10010
10024	20030	20021	20021	10025	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10025	20060	20035	20035	10058	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	10020	20011	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  negs x0, x1, asr #17
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	30030	30101	30101	20106	789311	20105	20212	20210	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20205	30060	30115	30115	20141	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	20212	30001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	30030	30011	30011	0	0	20015	0	789378	20015	20032	20020	30001	20010
20024	30030	30011	30011	0	0	20010	0	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	0	0	20010	0	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	0	0	20010	0	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	0	0	20010	0	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	0	0	20010	0	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	0	0	20010	0	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	0	0	20010	0	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	0	0	20010	0	789438	20010	20020	20020	30001	20010
20024	30030	30011	30011	0	0	20010	0	789438	20010	20020	20020	30001	20010

Test 4: throughput

Count: 8

Code:

  negs x0, x8, asr #17
  negs x1, x8, asr #17
  negs x2, x8, asr #17
  negs x3, x8, asr #17
  negs x4, x8, asr #17
  negs x5, x8, asr #17
  negs x6, x8, asr #17
  negs x7, x8, asr #17

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	53404	160114	160114	80123	1099808	80123	80224	80224	160014	80100
80204	53417	160114	160114	80123	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	80224	160014	80100
80205	53438	160168	160168	80164	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	80224	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	80224	160014	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	53385	160039	160039	80046	0	1107842	0	0	80048	80048	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	0	80020	80020	0	0	80020	160011	80010
80025	53413	160090	160090	80088	0	1104624	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1107514	0	0	80086	80086	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1107726	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	0	80020	80020	0	0	80020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	0	80020	80020	0	0	80020	160011	80010

NEGS (register, asr, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations