Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MVN (register, 32-bit)

Test 1: uops

Code:

  mvn w0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000

Test 2: Latency 1->2

Code:

  mvn w0, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	259416	10107	10214	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10214	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	259528	10030	10038	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010

Test 3: throughput

Count: 8

Code:

  mvn w0, w8
  mvn w1, w8
  mvn w2, w8
  mvn w3, w8
  mvn w4, w8
  mvn w5, w8
  mvn w6, w8
  mvn w7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80205	26942	80158	80158	80172	240360	80120	80222	80224	80015	80100
80204	26760	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240504	80171	80276	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80276	80057	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	28074	80037	80037	80042	258817	80044	80048	80020	80011	80010
80024	26781	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26716	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26865	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26717	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010