Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PACIZA

Test 1: uops

Code:

  paciza x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	? int output thing (e9)	? int retires (ef)
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000

Test 2: Latency 1->1

Code:

  paciza x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10205	60058	10204	10204	10211	530425	10211	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	60029	10021	10021	10020	529785	10020	20	20	0	0	10011	0	0	10010
10024	60029	10021	10021	10020	529785	10020	20	20	0	0	10011	0	0	10010
10024	60029	10021	10021	10020	529785	10020	20	20	0	0	10014	0	0	10010
10024	60029	10021	10021	10020	529785	10020	20	20	0	0	10011	0	0	10010
10024	60029	10021	10021	10020	529785	10020	20	20	0	0	10011	0	0	10010
10024	60029	10021	10021	10020	529785	10020	20	20	0	0	10011	0	0	10010
10024	60029	10021	10021	10020	529785	10020	20	20	0	0	10011	0	0	10010
10024	60029	10021	10021	10020	529785	10020	20	20	0	0	10011	0	0	10010
10024	60029	10021	10021	10020	529785	10020	20	20	0	0	10011	0	0	10010
10024	60029	10021	10021	10020	529785	10020	20	20	0	0	10011	0	0	10010

Test 3: throughput

Count: 8

Code:

  paciza x0
  paciza x1
  paciza x2
  paciza x3
  paciza x4
  paciza x5
  paciza x6
  paciza x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	160030	80201	80201	80202	1360481	80202	200	200	80101	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	80101	80100
80204	160030	80201	80201	80202	1360430	80202	200	200	80101	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	80101	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	80111	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	80101	80100
80204	160030	80201	80201	80202	1360573	80220	200	200	80101	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	80101	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	80101	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	80101	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	160030	80021	80021	0	0	80022	0	1359890	80022	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010