Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CRC32H

Test 1: uops

Code:

  crc32h w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000

Test 2: Latency 1->2

Code:

  crc32h w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204300301010110101101002601441010010206202161000110100
10204300301010110101101002601561010010208202121000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10205300601010610106101142601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024300301002110021100202599071002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010

Test 3: Latency 1->3

Code:

  crc32h w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204300301010110101101000260150010100102060202121000110100
10204300301010110101101000260156010100102080202161000110100
10204300301010110101101000260156010100102080202161000110100
10204300301010110101101000260156010100102080202161000110100
10205300601010610106101140260156010100102080202161000110100
10204300301010110101101000260156010100102080202161000110100
10204300301010110101101000260156010100102080202161000110100
10204300301010110101101000260156010100102080202161000110100
10204300301010110101101000260156010100102080202161000110100
10204300301010110101101000260156010100102080202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024300301002110021100202599071002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202600191003410043200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010

Test 4: throughput

Count: 8

Code:

  crc32h w0, w8, w9
  crc32h w1, w8, w9
  crc32h w2, w8, w9
  crc32h w3, w8, w9
  crc32h w4, w8, w9
  crc32h w5, w8, w9
  crc32h w6, w8, w9
  crc32h w7, w8, w9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802048004480104801048010524031580105802101602208000480100
802048003480104801048010524031580105802121602248000480100
802048003480104801048010524031580105802121602248000480100
802048003480104801048010524031580105802121602248000480100
802058006680120801208012424031580105802121602248000480100
802048003480104801048010524031580105802121602248000480100
802048003480104801048010524031580105802121602248000480100
802048003480104801048010524031580105802121602748002080100
802048003480104801048010524031580105802121602248000480100
802048003480104801048010524031580105802121602248000480100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80024800578002580025800260240060008002080020001600208001180010
80024800328002180021800200240060008002080020001600208001180010
80024800328002180021800200240060008002080020001600208001180010
80024800328002180021800200240060008002080020001600208001180010
80024800328002180021800200240132008004580057001600208001180010
80024800328002180021800200240060008002080020001600208001180010
80024800328002180021800200240060008002080020001600208001180010
80025800678004180041800450240060008002080020001600208001180010
80024800328002180021800200240060008002080020001600208001180010
80024800328002180021800200240060008002080020001600208001180010