Icestorm: MVN (register, asr, 64-bit) measurements

Code:

  mvn x0, x0, asr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000

Test 2: Latency 1->2

Code:

  mvn x0, x0, asr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	529143	10104	10210	10212	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	10212	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	10212	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	10212	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	10212	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	10212	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	10212	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	10212	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	10212	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	10212	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529197	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	20011	10010

Test 3: throughput

Count: 8

Code:

  mvn x0, x8, asr #17
  mvn x1, x8, asr #17
  mvn x2, x8, asr #17
  mvn x3, x8, asr #17
  mvn x4, x8, asr #17
  mvn x5, x8, asr #17
  mvn x6, x8, asr #17
  mvn x7, x8, asr #17

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	53429	160118	160118	80131	1361779	80340	80448	80236	160017	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80288	160062	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80234	160017	80100
80204	53404	160117	160117	80130	1360566	80130	80236	80236	160017	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80236	160017	80100
80204	53404	160117	160117	80130	1362107	80333	80439	80236	160017	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80236	160017	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80236	160017	80100
80204	53404	160117	160117	80130	1360838	80130	80236	80236	160017	80100
80204	53404	160117	160117	80130	1362081	80338	80443	80236	160017	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	53378	160039	160039	80051	1359975	80051	80056	80056	0	0	160029	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1360238	80067	80072	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1360560	80099	80108	108616	20944	396	173075	9118	177	95382
80024	53371	160021	160021	80020	1359903	80020	80020	80058	0	0	160029	0	0	80010

MVN (register, asr, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations