Icestorm: CCMP (register, 32-bit) measurements

Code:

  ccmp w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001
1004	1030	1001	1001	1000	25183	1000	1000	3000	1001
1004	1030	1001	1001	1000	25192	1000	1000	3000	1001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  ccmp w0, w1, #0, hi
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519752	20147	20258	40228	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519866	20148	20260	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100
20204	20030	20101	20101	20108	520019	20152	20260	40232	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  ccmp w0, w1, #0, hi
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0475

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519328	20107	20214	40232	20001	10100
20204	20331	20233	20233	20377	523288	20464	20586	40797	20121	10100
20204	20346	20229	20229	20374	523666	20506	20626	41066	20192	10100
20204	20374	20248	20248	20416	522834	20416	20544	41246	20234	10100
20204	20279	20208	20208	20329	523285	20459	20582	41055	20192	10100
20204	20401	20250	20250	20417	523288	20460	20579	40976	20171	10100
20204	20278	20210	20210	20330	523283	20505	20636	40974	20170	10100
20204	20524	20313	20313	20548	522342	20371	20492	40796	20127	10100
20204	20524	20313	20313	20548	523303	20460	20579	40882	20149	10100
20204	20477	20294	20294	20506	523739	20507	20639	41174	20213	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519516	20018	20034	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	40020	20001	10010

Test 4: Latency 3->3

Code:

  ccmp w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10208	254709	10208	10208	30242	10101	100
10204	10030	10201	10201	10212	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	30224	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	255005	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30059	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	30020	10011	10

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ccmp w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, w1, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7889

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	63213	160115	160115	160120	686407	160118	160218	240233	160015	100
160204	63145	160113	160113	160117	689534	160118	160220	240230	160015	100
160204	63087	160112	160112	160118	688308	160120	160220	240224	160012	100
160204	63082	160112	160112	160118	689796	160118	160220	240230	160014	100
160204	63096	160117	160117	160121	672010	160116	160217	240230	160015	100
160204	63112	160112	160112	160118	685997	160118	160220	240224	160010	100
160205	62704	160148	160148	160154	688958	160120	160220	240230	160014	100
160204	63129	160112	160112	160118	688458	160120	160224	240230	160015	100
160204	63114	160109	160109	160118	688958	160120	160220	240230	160013	100
160204	63129	160112	160112	160118	689253	160120	160220	240230	160012	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7831

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	64562	160023	160023	160027	692247	160027	160038	240047	160011	10
160024	63217	160023	160023	160030	670623	160010	160020	240020	160001	10
160024	62668	160011	160011	160010	671578	160010	160020	240020	160001	10
160024	62515	160011	160011	160010	669902	160010	160020	240020	160001	10
160024	62666	160011	160011	160010	671483	160010	160020	240020	160001	10
160024	62507	160011	160011	160010	669982	160010	160020	240020	160001	10
160024	62671	160011	160011	160010	671751	160071	160082	240020	160001	10
160024	62527	160011	160011	160010	670286	160010	160020	240020	160001	10
160024	62669	160011	160011	160010	672033	160010	160020	240020	160001	10
160024	62567	160011	160011	160010	670569	160010	160020	240020	160001	10

Test 6: throughput

Count: 4

Code:

  fcmp s0, s0
  ccmp w0, w1, #0, hi
  ccmp w0, w1, #0, hi
  ccmp w0, w1, #0, hi
  ccmp w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24003	50110	40106	10004	40117	10005	315434	40017	50118	40214	10004	120242	20008	40003	100
50204	23994	50103	40101	10002	40112	10004	315122	40017	50118	40214	10004	120227	20006	40001	100
50204	24004	50106	40103	10003	40112	10004	315063	40013	50112	40209	10003	120236	20008	40001	100
50204	23982	50104	40101	10003	40109	10003	315026	40017	50116	40212	10004	120227	20006	40001	100
50204	23981	50104	40101	10003	40112	10004	315105	40016	50120	40216	10004	120236	20008	40001	100
50204	24000	50103	40101	10002	40112	10004	314993	40013	50112	40209	10003	120227	20006	40003	100
50204	24004	50106	40103	10003	40112	10004	315509	40018	50116	40212	10004	120236	20008	40002	100
50204	23988	50104	40101	10003	40109	10003	315436	40017	50116	40212	10004	120236	20008	40001	100
50204	23967	50103	40101	10002	40109	10003	315898	40017	50116	40212	10004	120332	20022	40028	100
50204	23993	50103	40101	10002	40109	10003	314891	40012	50112	40209	10003	120248	20008	40007	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24255	50012	40011	10001	40016	10002	316440	40017	50028	40034	10004	120020	20000	40001	10
50024	23991	50011	40011	10000	40010	10000	315828	40000	50010	40020	10000	120020	20000	40001	10
50024	23962	50011	40011	10000	40010	10000	316838	40000	50010	40020	10000	120020	20000	40001	10
50024	23984	50011	40011	10000	40010	10000	316679	40000	50010	40020	10000	120020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	316186	40000	50010	40020	10000	120020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	315708	40000	50010	40020	10000	120020	20000	40001	10
50024	23975	50011	40011	10000	40010	10000	316012	40000	50010	40020	10000	120020	20000	40001	10
50024	23970	50011	40011	10000	40010	10000	316365	40000	50010	40020	10000	120020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	315746	40000	50010	40020	10000	120020	20000	40001	10
50024	23978	50011	40011	10000	40010	10000	316301	40000	50010	40020	10000	120020	20000	40001	10

Test 7: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  ccmp w0, w1, #0, hi
  ccmp w0, w1, #0, hi
  ccmp w0, w1, #0, hi
  ccmp w0, w1, #0, hi
  ccmp w0, w1, #0, hi
  ccmp w0, w1, #0, hi
  ccmp w0, w1, #0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5568

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	38907	80106	80106	0	0	80113	0	550439	80117	80218	210236	0	0	80006	0	0	100
80204	38902	80103	80103	0	0	80112	0	549992	80111	80212	210230	0	0	80003	0	0	100
80204	38969	80103	80103	0	0	80111	0	550563	80111	80212	210230	0	0	80005	0	0	100
80204	38990	80105	80105	0	0	80114	0	548392	80114	80216	210230	0	0	80003	0	0	100
80204	39003	80104	80104	0	0	80111	0	549137	80111	80212	210242	0	0	80004	0	0	100
80204	38985	80103	80103	0	0	80111	0	549902	80111	80212	210242	0	0	80006	0	0	100
80204	38974	80104	80104	0	0	80114	0	550563	80111	80212	210353	0	0	80037	0	0	100
80204	38899	80105	80105	0	0	80113	0	550985	80108	80208	210242	0	0	80007	0	0	100
80204	38967	80107	80107	0	0	80116	0	546806	80116	80217	210257	0	0	80011	0	0	100
86310	46464	85242	83048	23	2171	82850	23	547999	80119	80220	210245	0	0	80011	0	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5557

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	39083	80030	80030	80039	0	547374	0	80020	80020	0	210020	80011	10
80024	38881	80021	80021	80020	0	549057	0	80020	80020	0	210020	80011	10
80024	38911	80021	80021	80020	0	545323	0	80020	80020	0	210020	80011	10
80024	38930	80021	80021	80020	0	548904	0	80020	80020	0	210020	80011	10
80024	38892	80021	80021	80020	0	547401	0	80020	80020	0	210020	80011	10
80024	38901	80021	80021	80020	0	547667	0	80020	80020	0	210020	80011	10
80024	38927	80021	80021	80020	0	546571	0	80020	80020	0	210020	80011	10
80024	38861	80021	80021	80020	0	545450	0	80020	80020	0	210020	80011	10
80024	38905	80021	80021	80020	0	545493	0	80020	80020	0	210020	80011	10
80024	38928	80021	80021	80020	0	548621	0	80020	80020	0	210020	80011	10

CCMP (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations