Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDS (sxtw, 32-bit)

Test 1: uops

Code:

  adds w0, w0, w1, sxtw
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000

Test 2: Latency 1->2

Code:

  adds w0, w0, w1, sxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101082516761010910210202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282532011002810028200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010

Test 3: Latency 1->3

Code:

  adds w0, w1, w0, sxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101082515981010810210202121000110100
10204100301010110101101092517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101072517741010810208202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282532561002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010

Test 4: Latency 4->2

Chain cycles: 1

Code:

  adds w0, w1, w2, sxtw
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204200302010120101201075194162010720212302182000120100
20204200302010120101201075194342010720214302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024200302001120011200185194952001820036300442000120010
20024200302001120011200175195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010

Test 5: Latency 4->3

Chain cycles: 1

Code:

  adds w0, w1, w2, sxtw
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20205200602011520115201485190762010820214302212000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302902001520100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024200302001120011200185195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20025200602002520025200595195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010

Test 6: throughput

Count: 8

Code:

  adds w0, w8, w9, sxtw
  adds w1, w8, w9, sxtw
  adds w2, w8, w9, sxtw
  adds w3, w8, w9, sxtw
  adds w4, w8, w9, sxtw
  adds w5, w8, w9, sxtw
  adds w6, w8, w9, sxtw
  adds w7, w8, w9, sxtw
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5010

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802044008480111801118011424034580115802161602328001280100
802044008780112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602968004180100
802044011780109801098011224034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800244008880032800328003524011080035800361600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010