Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDP (signed offset, 32-bit)

Test 1: uops

Code:

  ldp w0, w1, [x6, #8]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
200568010211102010005188100020002000110001000
200454310011100010005188100020002000110001000
200454310011100010005188100020002000110001000
200454310011100010005188100020002000110001000
200454310011100010005188100020002000110001000
200454310011100010005188100020002000110001000
200454310011100010005188100020002000110001000
200454310011100010005188100020002000110001000
200454310011100010005188100020002000110001000
200454310011100010005188100020002000110001000

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp w0, w1, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502067018840118301151000330164100031857447710716040106302122000806022420008300021000040100
502047004340102301021000030103100561864995713607040291303672011306022420008300021000040100
502057015840111301091000230135100031857494710717040106302122000806022420008300021000040100
502047004040102301021000030103100031858316710962040106302122000806022420008300021000040100
502047004040102301021000030103100031858289710951040106302122000806022420008300021000040100
502047004040102301021000030103100031858289710951040106302122000806022420008300021000040100
502047004040102301021000030103100151858647711084040152302502003406022420008300021000040100
502047004040102301021000030103100031858289710951040106302122000806030020034300081000040100
502047004040102301021000030103100031858289710951040106302122000806022420008300021000040100
502047004040102301021000030103100031858289710951040106302122000806022420008300021000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
500257014740018300171000130040100001857783711409400103002020000600202000003000310000040010
500257007740021300191000230045100001859562712077400103002020000600202000003000310000040010
500247005240013300131000030010100001858949711975400103002020000600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010
500247004940013300131000030010100001858976711985400103002020000600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000600202000003000310000040010
500247004740013300131000030010100001858949711975400103002020000601202003403000910000040010
500247006940013300131000030010100001859030712005400103002020000600202000003000310000040010

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp w0, w1, [x6, #8]
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5020570147401083010710001301301000318569717105474010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031001518616087122954015030250200346022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031001518588247111344015030250200346022420008300031000040100
5020470050401033010310000301031000318584787110214010630212200086030020034300091000040100
5246591462421943139110803314011000318588927111334010630210200086022420008300031000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5002570165400183001710001300401000318593927120484001630032200086002020000300021000040010
5002470040400123001210000300101000018587607119054001030020200006002020000300021000040010
5002470040400123001210000300101000018587607119054001030020200006002020000300021000040010
5002470040400123001210000300101000018587607119054001030020200006002020000300021000040010
5002470040400123001210000300101000018587877119174001030020200006002020000300021000040010
5002470042400123001210000300101000018587607119054001030020200006002020000300021000040010
5002470040400123001210000300101000018587607119054001030020200006002020000300021000040010
5002470040400123001210000300101000018608667127674001030020200006002020000300021000040010
5002470048400123001210000300101000018588147119274001030020200006002020000300021000040010
5002470040400123001210000300101000018587607119054001030020200006002020000300021000040010

Test 4: throughput

Count: 8

Code:

  ldp w0, w1, [x6, #8]
  ldp w0, w1, [x6, #8]
  ldp w0, w1, [x6, #8]
  ldp w0, w1, [x6, #8]
  ldp w0, w1, [x6, #8]
  ldp w0, w1, [x6, #8]
  ldp w0, w1, [x6, #8]
  ldp w0, w1, [x6, #8]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160205402548013710180036100800123002507268011220016002420016002418000080100
160204401078010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160205403258013710180036100800123002671538011220016002420016002418000080100
160204401528010910180008100800123002513158011220016002420016002418000080100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1600254056080046118003510800123024373480022201600242016000018000080010
1600244011780011118000010800003055908980010201600002016000018000080010
1600244006280011118000010800003056300880010201600002016000018000080010
1600244005980011118000010800003038429080010201600002016000018000080010
1600244005580011118000010800003038429080010201600002016000018000080010
1600244005580011118000010800003038429080010201600002016000018000080010
1600244005580011118000010800003038429080010201600002016000018000080010
1600244005580011118000010800003038429080010201600002016011218000080010
1600244006780011118000010800003052018080010201600002016000018000080010
1600244005580011118000010800003038429080010201600002016000018000080010