Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STP (64-bit)

Test 1: uops

Code:

  stp x0, x1, [x6]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
1005115610191101810001704310001000300011000
1004104710011100010001688310001000300011000
1004103910011100010001688310001000300011000
1004103910011100010001688310001000300011000
1004103910011100010001688310001000300011000
1004103910011100010001688310001000300011000
1004103910011100010001688310001000300011000
1004103910011100010001688310001000300011000
1004103910011100010001688310001000300011000
1004103910011100010001688310001000300011000

Test 2: throughput

Count: 8

Code:

  stp x0, x1, [x6]
  stp x0, x1, [x6]
  stp x0, x1, [x6]
  stp x0, x1, [x6]
  stp x0, x1, [x6]
  stp x0, x1, [x6]
  stp x0, x1, [x6]
  stp x0, x1, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
802058014980119101800181008003630013601278013620080051200240024180000100
802048004780101101800001008000130013600828010120080008200240024180000100
802048004780101101800001008000130013600468010120080008200240024180000100
802048004780101101800001008000130013600468010120080008200240024180000100
802048004780101101800001008000130013600468010120080008200240024180000100
802048004780101101800001008000330013600258010320080010200240024180000100
802048005080101101800001008000130013600468010120080008200240024180000100
802048004780101101800001008000130013600468010120080008200240024180000100
802048004780101101800001008000130013600468010120080008200240024180000100
802048004780101101800001008000130013600468010120080008200240024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
800258014780029118001810800373013601688004720800522024000018000010
800248004780011118000010800003013598838001020800002024000018000010
800248004780011118000010800003013598838001020800002024000018000010
800248004780011118000010800003013598838001020800002024000018000010
800248004780011118000010800003013598838001020800002024000018000010
800248004780011118000010800003013598838001020800002024000018000010
800248004780011118000010800003013598838001020800002024000018000010
800248004780011118000010800003013598838001020800002024000018000010
800248004780011118000010800003013598838001020800002024000018000010
800248004780011118000010800003013598838001020800002024000018000010