Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMN (immediate, 32-bit)

Test 1: uops

Code:

  cmn w0, #3

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	501	1001	1001	1000	3000	1000	1000	1000	1001
1004	396	1001	1001	1000	3000	1000	1000	1000	1001
1004	395	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	395	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	400	1001	1001	1000	3000	1000	1000	1000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  cmn w0, #3
  cset x0, cc

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519339	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519454	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20209	20085	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20205	20085	10010

Test 3: throughput

Count: 8

Code:

  cmn w0, #3
  cmn w0, #3
  cmn w0, #3
  cmn w0, #3
  cmn w0, #3
  cmn w0, #3
  cmn w0, #3
  cmn w0, #3

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3636

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29185	80114	80114	80118	240357	80119	80220	80218	80014	100
80204	29177	80113	80113	80118	240357	80119	80220	80220	80013	100
80204	29082	80115	80115	80119	240354	80118	80220	80220	80013	100
80204	29120	80112	80112	80117	240354	80118	80220	80220	80015	100
80204	29084	80112	80112	80117	240351	80117	80220	80220	80013	100
80204	29072	80112	80112	80117	240357	80119	80220	80220	80013	100
80204	29051	80115	80115	80119	240354	80118	80220	80220	80013	100
80204	29166	80113	80113	80118	240354	80118	80220	80220	80012	100
80204	29066	80113	80113	80118	240351	80117	80220	80220	80015	100
80204	29046	80112	80112	80117	240357	80119	80220	80220	80013	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3631

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	30097	80035	80035	80039	240122	80039	80040	80042	80024	10
80024	29238	80021	80021	80020	240070	80020	80020	80020	80011	10
80024	29707	80034	80034	80038	240135	80039	80040	80042	80027	10
80024	29094	80035	80035	80040	240073	80020	80020	80020	80011	10
80025	29075	80074	80074	80079	240107	80020	80020	80080	80065	10
80024	29086	80035	80035	80039	240060	80020	80020	80020	80011	10
80024	29038	80021	80021	80020	240076	80020	80020	80020	80011	10
80024	28992	80021	80021	80020	240060	80020	80020	80020	80011	10
80024	28921	80021	80021	80020	240084	80020	80020	80084	80065	10
80024	29012	80021	80021	80020	240070	80020	80020	80020	80011	10