Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MSUB (32-bit)

Test 1: uops

Code:

  msub w0, w0, w1, w2
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000
100430301001100110002585610001000300010011000

Test 2: Latency 1->2

Code:

  msub w0, w0, w1, w2
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204300301010110101101002602471011410230302181000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10205300601010610106101142601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024300301002110021100202599071002010030300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202600191003410048300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010

Test 3: Latency 1->3

Code:

  msub w0, w1, w0, w2
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204300301010110101101002601561010010208302181000110100
10204300301010110101101002601501010010206302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100
10204300301010110101101002601561010010208302241000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10025300601002610026100342599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010
10024300301002110021100202599161002010020300201001110010

Test 4: Latency 1->4

Code:

  msub w0, w1, w2, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0034

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
1020410054101041010410105303151010510210302301000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100
1020410034101041010410105303151010510212302361000410100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0032

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
1002410035100251002510026300781002610034300561001510010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020301321004510056300201001110010
1002410032100211002110020300601002010020300201001110010
1002410032100211002110020300601002010020301401003110010
1002410032100211002110020300601002010020300201001110010

Test 5: throughput

Count: 8

Code:

  msub w0, w8, w9, w9
  msub w1, w8, w9, w9
  msub w2, w8, w9, w9
  msub w3, w8, w9, w9
  msub w4, w8, w9, w9
  msub w5, w8, w9, w9
  msub w6, w8, w9, w9
  msub w7, w8, w9, w9
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802048005480104801048010524031580105802122402368000480100
802048004480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122403088002080100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100
802048003480104801048010524031580105802122402368000480100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800248003580025800258002624006080020800202400208001180010
800248003280021800218002024006080020800202400208001180010
800248003280021800218002024006080020800202400208001180010
800248003280021800218002024006080020800202400208001180010
800248003280021800218002024006080020800202400208001180010
800248003280021800218002024006080020800202400208001180010
800248003280021800218002024006080020800202400208001180010
800248003280021800218002024006080020800202400208001180010
800248003280021800218002024006080020800202400208001180010
800248003280021800218002024006080020800202400208001180010