Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

BFC (64-bit)

Test 1: uops

Code:

  bfc x0, #3, #7
  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10041030100110011000300010001000100010011000
10041030100110011000300010001000100010011000
10041030100110011000300010001000100010011000
10041030100110011000300010001000100010011000
10041030100110011000300010001000100010011000
10041030100110011000300010001000100010011000
10041030100110011000300010001000100010011000
10041030100110011000300010001000100010011000
10041030100110011000300010001000100010011000
10041030100110011000300010001000100010011000

Test 2: Latency 1->1

Code:

  bfc x0, #3, #7
  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0034

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
1020410034101041010410105303151010510212102121000410100
1020410034101041010410105303151010510212102121000410100
1020410034101041010410105303151010510212102121000410100
1020410034101041010410105303151010510212102121000410100
1020410034101041010410105303151010510212102121000410100
1020410034101041010410105303151010510212102121000410100
1020410034101041010410105303151010510212102121000410100
1020410034101041010410105303151010510212102121000410100
1020410034101041010410105303151010510212102121000410100
1020410034101041010410105303151010510212102121000410100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
1002410068100251002510026300781002610032100201001110010
1002410030100211002110020300601002010020100201001110010
1002410030100211002110020300601002010020100201001110010
1002410030100211002110020300601002010020100201001110010
1002410030100211002110020300601002010020100201001110010
1002410030100211002110020300601002010020100201001110010
1002410030100211002110020300601002010020100201001110010
1002410030100211002110020300601002010020100201001110010
1002510065100391003910043300601002010020100201001110010
1002410030100211002110020300781002610032100201001110010

Test 3: throughput

Count: 8

Code:

  bfc x0, #3, #7
  bfc x1, #3, #7
  bfc x2, #3, #7
  bfc x3, #3, #7
  bfc x4, #3, #7
  bfc x5, #3, #7
  bfc x6, #3, #7
  bfc x7, #3, #7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80204800648010480104801052403158010580210802128000480100
80204800348010480104801052403158010580212802128000480100
80204800348010480104801052403158010580212802128000480100
80204800348010480104801052403158010580212802368001880100
80204800348010480104801052403158010580212802128000480100
80204800348010480104801052403158010580212802128000480100
80204800348010480104801052403158010580212802128000480100
80204800348010480104801052403158010580212802128000480100
80204800348010480104801052403158010580212802128000480100
80204800348010480104801052403158010580212802128000480100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
800248003580025800258002624006080020800208002000800110080010
800248003080021800218002024006080020800208002000800110080010
800248003080021800218002024006080020800208002000800110080010
800248003080021800218002024006080020800208002000800110080010
800248003080021800218002024012680043800568002000800110080010
800248003080021800218002024006080020800208002000800110080010
800248003080021800218002024006080020800208002000800110080010
800248003080021800218002024006080020800208002000800110080010
800248003080021800218002024006080020800208002000800110080010
800248003080021800218002024006080020800208002000800110080010