Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CRC32X

Test 1: uops

Code:

  crc32x w0, w0, x1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000

Test 2: Latency 1->2

Code:

  crc32x w0, w0, x1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
102043003010101101010101002601501010010206202121000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100
102053006010106101060101142601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024300301002110021100202599071002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010

Test 3: Latency 1->3

Code:

  crc32x w0, w1, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204300301010110101101002601441010010206202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024300301002110021100202599161002010028200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010

Test 4: throughput

Count: 8

Code:

  crc32x w0, w8, x9
  crc32x w1, w8, x9
  crc32x w2, w8, x9
  crc32x w3, w8, x9
  crc32x w4, w8, x9
  crc32x w5, w8, x9
  crc32x w6, w8, x9
  crc32x w7, w8, x9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80204800548010480104801050240315008010580210001604288009280100
80205800768012080120801240240315008010580212001602248000480100
80204800448010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204802218019480194801990240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204802208019280192801970240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204802188019280192801970240315008010580212001602728002080100
80204800348010480104801050240315008010580212001602248000480100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800248003580025800258002624018680064800831600468001580010
800248004380021800218002024006080020800201600208001180010
800248003280021800218002024013280045800571600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024013280045800561601008003180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010