Icestorm: STRB (pre-index) measurements

Code:

  strb w0, [x6, #8]!

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1268	2059	1041	1018	1040	1000	4677	17731	2000	1000	2000	1001	1000
1004	1070	2001	1001	1000	1000	1000	4761	18073	2000	1000	2000	1001	1000
1004	1074	2001	1001	1000	1000	1000	4761	17497	2000	1000	2000	1001	1000
1004	1066	2001	1001	1000	1000	1000	4761	18019	2000	1000	2000	1001	1000
1004	1094	2001	1001	1000	1000	1000	4761	17965	2000	1000	2000	1001	1000
1004	1075	2001	1001	1000	1000	1000	4761	17929	2000	1000	2000	1001	1000
1004	1092	2001	1001	1000	1000	1000	4761	18127	2000	1000	2000	1001	1000
1004	1074	2001	1001	1000	1000	1000	4761	17587	2000	1000	2000	1001	1000
1004	1097	2001	1001	1000	1000	1000	4761	17569	2000	1000	2000	1001	1000
1004	1100	2001	1001	1000	1000	1000	4761	18109	2000	1000	2000	1001	1000

Test 2: Latency 2->2

Code:

  strb w0, [x6, #8]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0150

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10209	11224	20404	10314	10090	10314	10002	43548	171835	20106	200	10008	200	20020	10005	10000	100
10204	10154	20104	10104	10000	10104	10002	43562	171943	20106	200	10008	200	20016	10004	10000	100
10204	10144	20104	10104	10000	10104	10002	43562	171943	20106	200	10008	200	20016	10004	10000	100
10204	10149	20104	10104	10000	10104	10002	43562	172159	20106	200	10008	200	20016	10004	10000	100
10204	10163	20104	10104	10000	10104	10001	43560	172210	20105	200	10008	200	20016	10004	10000	100
10204	10170	20104	10104	10000	10104	10002	43562	171943	20106	200	10008	200	20016	10004	10000	100
10204	10150	20104	10104	10000	10104	10002	43551	171835	20106	200	10008	200	20016	10004	10000	100
10204	10150	20104	10104	10000	10104	10002	43551	171835	20106	200	10008	200	20016	10004	10000	100
10204	10150	20104	10104	10000	10104	10002	43551	171835	20106	200	10008	200	20016	10004	10000	100
10204	10150	20104	10104	10000	10104	10002	43562	171943	20106	200	10008	200	20016	10004	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0118

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10029	11387	20307	10217	10090	10218	10001	42964	171166	20015	20	10008	20	20000	10001	10000	10
10024	10133	20014	10014	10000	10014	10000	43075	171109	20010	20	10000	20	20000	10001	10000	10
10024	10102	20011	10011	10000	10010	10000	43075	171073	20010	20	10000	20	20000	10001	10000	10
10024	10102	20011	10011	10000	10010	10000	43075	171073	20010	20	10000	20	20000	10001	10000	10
10024	10165	20011	10011	10000	10010	10000	43079	172207	20010	20	10000	20	20000	10001	10000	10
10024	10164	20011	10011	10000	10010	10000	43079	172189	20010	20	10000	20	20000	10001	10000	10
10024	10164	20011	10011	10000	10010	10000	43079	172189	20010	20	10000	20	20000	10001	10000	10
10024	10164	20011	10011	10000	10010	10000	43079	172207	20010	20	10000	20	20000	10001	10000	10
10024	10164	20011	10011	10000	10010	10000	43079	172207	20010	20	10000	20	20000	10001	10000	10
10024	10165	20011	10011	10000	10010	10000	43079	172189	20010	20	10000	20	20000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  strb w0, [x6, #8]!
  strb w0, [x7, #8]!
  strb w0, [x8, #8]!
  strb w0, [x9, #8]!
  strb w0, [x10, #8]!
  strb w0, [x11, #8]!
  strb w0, [x12, #8]!
  strb w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0013

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	80979	160401	80311	80090	80311	80002	240312	1361062	160106	200	80008	200	160016	80005	80000	100
80204	80106	160105	80105	80000	80104	80002	240312	1361111	160106	200	80008	200	160016	80005	80000	100
80205	80157	160155	80138	80017	80142	80002	240312	1361062	160106	200	80008	200	160016	80005	80000	100
80204	80106	160105	80105	80000	80104	80002	240312	1361111	160106	200	80008	200	160016	80005	80000	100
80204	80106	160105	80105	80000	80104	80002	240312	1361111	160106	200	80008	200	160016	80005	80000	100
80204	80106	160105	80105	80000	80104	80002	240312	1361111	160106	200	80008	200	160016	80005	80000	100
80204	80106	160105	80105	80000	80104	80002	240312	1361255	160106	200	80008	200	160016	80005	80000	100
80204	80106	160105	80105	80000	80104	80002	240312	1361111	160106	200	80008	200	160016	80005	80000	100
80204	80106	160105	80105	80000	80104	80002	240312	1361111	160106	200	80008	200	160096	80040	80000	100
80204	80106	160105	80105	80000	80104	80002	240312	1361111	160106	200	80008	200	160016	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	80929	160305	80215	80090	80214	80002	240042	1360157	160016	20	80008	20	160000	80001	80000	10
80024	80053	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80025	80128	160065	80048	80017	80052	80000	240030	1360102	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160096	80037	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10

STRB (pre-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations